Question 5 of 5: Common-source MOSFET amplifier — bias design and gain
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Closed-book national examination, 3 hours, five questions each worth 20 marks (answer all five). Op-amps ideal, supplies ±15 V unless stated.
Reference texts. A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (diodes Ch. 4; MOSFET amplifiers Ch. 5–7; BJT amplifiers Ch. 6–7; op-amps & instrumentation amplifier Ch. 2). C. K. Alexander & M. Sadiku, Fundamentals of Electric Circuits, 7th ed. (nodal analysis, bridge networks Ch. 3).
Question 5: Common-source MOSFET amplifier — bias design and gain
[Figure not reproduced. See the official exam paper or the cited reference text.]
G1/RG2 divider; source resistor RS is not bypassed; output at the drain coupled through C₂ to RL." style="max-width:460px;width:100%;height:auto">
Question 5 — single-stage common-source amplifier. Gate biased by the RG1/RG2 divider; source resistor RS is not bypassed; output at the drain coupled through C₂ to RL.
Given. An n-channel common-source stage, $\lambda=0$ (so $r_o=\infty$); the drawn circuit shows no bypass capacitor across RS, so the source is degenerated at signal frequencies.
Given data
Parameter
Value
$V_{TH}$, $K$, λ
1 V, 4 mA/V², 0
$V_{DD}$, $I_D$
15 V, 0.5 mA
$V_S$, $V_D$
3.5 V, 6 V
$R_{in}$, $R_1$, $R_L$ (part b)
1.67 MΩ, 100 kΩ, 200 kΩ
Find. RG1, RG2, RS, RD (part a); the overall gain $v_{out}/v_i$ (part b).
Approach. Read RS and RD straight off the DC operating point, get VGS from the square law, split the gate divider using VG and the required Rin, then combine the input divider with the degenerated CS gain.
Source and drain resistors (part a). Directly from the node voltages and drain current:$$R_S=\frac{V_S}{I_D}=\frac{3.5}{0.5\ \text{mA}}=\boxed{7\ \text{k}\Omega},\quad R_D=\frac{V_{DD}-V_D}{I_D}=\frac{9}{0.5\ \text{mA}}=\boxed{18\ \text{k}\Omega}.$$
Gate–source voltage. From the saturation square law $I_D=\tfrac12 K(V_{GS}-V_{TH})^2$:$$V_{GS}=V_{TH}+\sqrt{\frac{2I_D}{K}}=1+\sqrt{\frac{2(0.5\ \text{mA})}{4\ \text{mA/V}^2}}=1.5\ \text{V}.$$ Check saturation: $V_{DS}=V_D-V_S=2.5\ \text{V}\ge V_{GS}-V_{TH}=0.5\ \text{V}$ — confirmed.
Gate bias divider. $V_G=V_{GS}+V_S=5\ \text{V}$, so $\dfrac{R_{G2}}{R_{G1}+R_{G2}}=\dfrac{V_G}{V_{DD}}=\dfrac13$. Combining with the target $R_{in}=R_{G1}\parallel R_{G2}=1.67\ \text{M}\Omega$ gives$$R_{G1}=\boxed{5\ \text{M}\Omega},\qquad R_{G2}=\boxed{2.5\ \text{M}\Omega}$$ (which indeed parallel to 1.67 MΩ).
Gain from gate to output. With RS unbypassed and $r_o=\infty$, the stage is source-degenerated:$$A_v=\frac{v_{out}}{v_{in}}=-\frac{g_m\,(R_D\parallel R_L)}{1+g_mR_S}=-\frac{(2\ \text{mA/V})(16.5\ \text{k}\Omega)}{1+(2\ \text{mA/V})(7\ \text{k}\Omega)}=-\frac{33.0}{15}=-2.20\ \text{V/V},$$ where $R_D\parallel R_L=18\parallel200=16.5\ \text{k}\Omega$ and $g_mR_S=14$.
Add the input divider. The source $v_i$ drives the gate through R₁ into $R_{in}$, so $v_{in}/v_i=R_{in}/(R_{in}+R_1)=1.67/1.77=0.943$. Overall:$$\frac{v_{out}}{v_i}=0.943\times(-2.20)=\boxed{-2.08\ \text{V/V}}.$$
Check: the drawn circuit has no bypass capacitor across RS, so the stage is degenerated and the gain is only about −2 V/V. A bypassed source would instead give $|A_v|=g_m(R_D\parallel R_L)\approx33$ — roughly 15× larger. The unbypassed reading is the one consistent with the schematic.
