Bias Design and Small-Signal Performance of an NMOS Cascode: 22-Elec-B5 Advanced Electronics, December 2016, Q2

Question 2: Bias Design and Small-Signal Performance of an NMOS Cascode (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A cascode: \(M_1\) is the common-source device (gate at \(V_{G1}\), source through \(R_S\) to \(-V_{SS}\) with an infinite bypass capacitor), and \(M_2\) is the common-gate device stacked on top of it, its gate held at \(V_{G2}\) and bypassed to ground. The chain \(R_1,R_2,R_3\) runs from \(+V_{DD}\) to ground and taps off both gate voltages.

Quantity	Symbol	Value
Threshold voltage	\(V_{TH}\)	1.2 V
Transconductance parameter	\(K\)	0.8 mA/V\(^2\)
Channel-length modulation	\(\lambda\)	0 (so \(r_o=\infty\))
Supplies	\(V_{DD},\ V_{SS}\)	5 V, 5 V
Target drain current	\(I_{DS1}=I_{DS2}\)	0.4 mA
Target drain–source voltages	\(V_{DS1}=V_{DS2}\)	2.5 V
Source resistor	\(R_S\)	10 kΩ
Bias chain total	\(R_1+R_2+R_3\)	300 kΩ
Load	\(R_L\)	2 kΩ

Find. The four bias resistors \(R_D,R_1,R_2,R_3\) that place the stage at the stated operating point, then \(v_{out}/v_{in}\), \(R_{in}\) and \(R_{out}\).

Question 2. NMOS cascode. The bias chain R1-R2-R3 sets both gate voltages; the source of M1 is bypassed, so v_gs1 = v_in.

Check: the drain resistor is drawn as \(R_D\) but is not given a value, while the Given list supplies an \(R_L=2\ \text{k}\Omega\) that appears nowhere in the schematic. The only self-consistent reading is that \(R_D\) is part of the design (it must be 2.5 kΩ to make \(V_{DS2}=2.5\ \text{V}\) with \(R_S=10\ \text{k}\Omega\) given) and that \(R_L\) is an external ac load hung on \(v_{OUT}\). Both the loaded and the unloaded gain are quoted below so either marking scheme is served.

Approach. Work the dc design from the bottom up — the source resistor fixes \(V_{S1}\), the square-law equation fixes the overdrive and hence every gate-to-source drop, and the two 2.5 V targets stack the remaining node voltages — then apply the small-signal model, remembering that \(\lambda=0\) makes the cascode device transparent to the gain.

Part (a) — get the overdrive from the square law. Both devices carry the same current because they are in series, so \[I_D=\tfrac{1}{2}K\,V_{OV}^{2}\ \Rightarrow\ V_{OV}=\sqrt{\frac{2I_D}{K}}=\sqrt{\frac{2(0.4\ \text{mA})}{0.8\ \text{mA/V}^2}}=1.00\ \text{V},\] \[\boxed{V_{GS1}=V_{GS2}=V_{TH}+V_{OV}=1.2+1.0=2.2\ \text{V}}\] The overdrive is the same for both devices only because they carry equal current and are identically sized; that is what allows the node voltages to be stacked mechanically in the next step.
Walk up the stack to fix every node voltage. The source resistor carries the whole drain current: \[V_{S1}=-V_{SS}+I_DR_S=-5+(0.4\ \text{mA})(10\ \text{k}\Omega)=-1.00\ \text{V}.\] Adding \(V_{GS1}\) gives the lower gate, adding \(V_{DS1}\) gives the intermediate node, and so on: \[V_{G1}=-1.0+2.2=1.20\ \text{V},\qquad V_{D1}=V_{S2}=-1.0+2.5=1.50\ \text{V},\] \[V_{G2}=1.5+2.2=3.70\ \text{V},\qquad V_{D2}=1.5+2.5=4.00\ \text{V}.\] Each device has \(V_{DS}=2.5\ \text{V}\) against an overdrive of 1.0 V, so both are 1.5 V clear of the triode boundary.
Size the drain resistor. The drop across \(R_D\) is whatever is left between the positive rail and the output node: \[R_D=\frac{V_{DD}-V_{D2}}{I_D}=\frac{5-4.00}{0.4\ \text{mA}}=\boxed{2.50\ \text{k}\Omega}\]
Split the 300 kΩ bias chain. The chain runs from \(+V_{DD}\) to ground and the gates draw no current, so a single current flows through all three resistors: \[I_{div}=\frac{V_{DD}}{R_1+R_2+R_3}=\frac{5\ \text{V}}{300\ \text{k}\Omega}=16.67\ \mu\text{A}.\] Each resistor is then simply its required voltage divided by that current: \[R_3=\frac{V_{G1}}{I_{div}}=\frac{1.20}{16.67\ \mu\text{A}}=72\ \text{k}\Omega,\quad R_2=\frac{V_{G2}-V_{G1}}{I_{div}}=\frac{2.50}{16.67\ \mu\text{A}}=150\ \text{k}\Omega,\] \[R_1=\frac{V_{DD}-V_{G2}}{I_{div}}=\frac{1.30}{16.67\ \mu\text{A}}=78\ \text{k}\Omega.\] \[\boxed{R_1=78\ \text{k}\Omega,\quad R_2=150\ \text{k}\Omega,\quad R_3=72\ \text{k}\Omega,\quad R_D=2.5\ \text{k}\Omega}\] The three values sum to exactly 300 kΩ, which is the arithmetic check the question builds in.
Part (b) — transconductance at the design point. Differentiating the square law, \[g_m=K\,V_{OV}=\frac{2I_D}{V_{OV}}=0.8\ \text{mA/V}.\] Both forms agree, which is a quick guard against having mixed up \(K\) with \(k'W/L\) conventions.
Voltage gain. The source of \(M_1\) is bypassed, so \(v_{gs1}=v_{in}\); the signal current \(g_mv_{in}\) passes straight through the cascode device into the drain node. With \(\lambda=0\) the resistance looking into \(M_2\)'s drain is infinite, so the only load is \(R_D\) in parallel with the external \(R_L\): \[A_v=\frac{v_{out}}{v_{in}}=-g_m\left(R_D\parallel R_L\right)=-0.8\ \text{mA/V}\times\left(2.5\parallel 2\right)\text{k}\Omega=-0.8\times 1.111,\] \[\boxed{A_v=-0.889\ \text{V/V}\ \ (\text{unloaded: } -g_mR_D=-2.00\ \text{V/V})}\] The cascode buys nothing in gain here — that is the lesson of the \(\lambda=0\) assumption. Its value is in the output resistance and in shielding \(M_1\)'s drain from the output swing, and a real device with a finite \(r_o\) would show that immediately.
Input resistance. Looking right from the source through the coupling capacitor, the gate itself draws nothing; \(R_3\) goes to ground and \(R_2\) goes to \(V_{G2}\), which is an ac ground because of its own bypass capacitor. \(R_1\) returns to the supply and so plays no ac part: \[R_{in}=R_2\parallel R_3=\frac{150\times 72}{150+72}=\boxed{48.6\ \text{k}\Omega}\]
Output resistance. With \(\lambda=0\) the cascode presents an open circuit at its drain, so \[R_{out}=R_D\parallel r_{o,\text{cascode}}=R_D\parallel\infty=\boxed{2.50\ \text{k}\Omega}\] In a real cascode this term would be roughly \(g_{m2}r_{o2}r_{o1}\) — megohms — and would still leave \(R_D\) in charge, which is exactly why cascodes are used with active loads rather than resistive ones.

Result	Symbol	Value
Overdrive / gate drive	\(V_{OV},\ V_{GS}\)	1.00 V, 2.20 V
Source, gate, intermediate and output nodes	\(V_{S1},V_{G1},V_{S2},V_{G2},V_{D2}\)	\(-1.00,\ 1.20,\ 1.50,\ 3.70,\ 4.00\) V
Drain resistor	\(R_D\)	2.50 kΩ
Bias chain	\(R_1,\ R_2,\ R_3\)	78 kΩ, 150 kΩ, 72 kΩ (sum 300 kΩ)
Transconductance	\(g_m\)	0.80 mA/V
Voltage gain (with \(R_L\) / unloaded)	\(v_{out}/v_{in}\)	\(-0.889\) / \(-2.00\) V/V
Input resistance	\(R_{in}\)	48.6 kΩ
Output resistance	\(R_{out}\)	2.50 kΩ

Topic. Square-law biasing of a MOSFET cascode and the small-signal consequences of \(\lambda=0\).

Key relations. Saturation current \(I_D=\tfrac12 K(V_{GS}-V_{TH})^2(1+\lambda V_{DS})\), saturation condition \(V_{DS}\ge V_{OV}\); \(g_m=KV_{OV}=2I_D/V_{OV}\); cascode output resistance \(R_{out}\approx g_{m2}r_{o2}r_{o1}\); a bypassed source gives \(A_v=-g_mR_L'\).

Why this works. Because gate current is zero, the three-resistor chain carries one current and the design collapses to arithmetic: pick the current, get the overdrive from the square law, and then simply stack the required drops from the negative rail upward. Nothing is iterative. On the signal side, stacking a common-gate device on a common-source device does not change the current that reaches the output node — it only changes the impedance seen there — so with an ideal current source in place of \(r_o\) the gain is set entirely by the resistive load.

Common pitfall. Writing \(g_m=2I_D/V_{OV}\) but then evaluating \(V_{OV}\) from \(I_D=KV_{OV}^2\) (missing the factor \(\tfrac12\)) makes the overdrive 0.707 V and every subsequent node voltage wrong; always take the square-law form from the sheet the paper supplies. The other frequent error is to "improve" the gain by adding the cascode's \(g_mr_o^2\) to the load — with a 2.5 kΩ drain resistor in parallel it changes the answer by far less than the third significant figure even when \(r_o\) is finite.

Source. A. S. Sedra & K. C. Smith, Microelectronic Circuits, 7th/8th ed., Ch. 5 (MOSFET square law and biasing) and Ch. 8 §8.5 (the cascode amplifier); B. Razavi, Design of Analog CMOS Integrated Circuits, Ch. 3.

Question 2 of 5: Bias Design and Small-Signal Performance of an NMOS Cascode

Question 2: Bias Design and Small-Signal Performance of an NMOS Cascode (20 marks)