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22-Elec-B5 Advanced Electronics · December 2016

Question 5 of 5: Miller (Pole-Splitting) Compensation of a Two-Pole Op Amp

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

07-Elec-B5 — Advanced Electronics — National Exams, December 2016 · 3 hours · CLOSED BOOK, any non-communicating calculator permitted · five questions, all to be answered, 20 marks each (100 marks total). Op-amps ideal and supplies ±15 V unless a question states otherwise; in schematics ground and chassis are common.

Reference texts for this subject:

  • A. S. Sedra & K. C. Smith, Microelectronic Circuits, 7th/8th ed. — Ch. 6–7 (BJT and MOS amplifier stages), Ch. 8 (cascodes and IC building blocks), Ch. 10 (frequency response), Ch. 11 (feedback, stability and frequency compensation), Ch. 12 (output stages and power amplifiers).
  • B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. — Ch. 3 (single-stage amplifiers and the cascode), Ch. 10 (stability and frequency compensation).
  • P. R. Gray, P. J. Hurst, S. H. Lewis & R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. — Ch. 8 (feedback) and Ch. 9 (frequency response and compensation).
  • B. Razavi, Fundamentals of Microelectronics, 2nd ed. — the worked-example convention (including \(V_T = 26\) mV) used by several questions in this subject's paper series.

Question 5: Miller (Pole-Splitting) Compensation of a Two-Pole Op Amp (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The equivalent circuit of the gain stage that carries both open-loop poles: node B (the input node, with \(C_1\) and its shunt resistance) and node C (the output node, with \(C_2\) and its shunt resistance), coupled by the transconductance \(g_m v_\pi\). A compensation capacitor \(C_f\) is to be connected between the two nodes.

QuantitySymbolValue
Input-node capacitance\(C_1\)100 pF
Output-node capacitance\(C_2\)5 pF
Stage transconductance\(g_m\)40 mA/V
Uncompensated first pole\(f_{P1}\)0.1 MHz
Uncompensated second pole\(f_{P2}\)1 MHz
Open-loop dc gain (from the plot)\(A_0\)100 dB \(=10^{5}\)
Worst-case feedback factor\(\beta\)1 (unity-gain follower)

Find. A value of \(C_f\) that makes the amplifier stable at \(\beta=1\), with justification; the resulting pole frequencies; and the resulting phase margin.

iS C1 R1 +vπ −BCf gm vπ CR2 C2 vO
Question 5. Equivalent circuit of the gain stage. Cf bridges the input and output nodes, so it is multiplied by the stage gain at node B and appears almost undiminished at node C.
Check: the drawing labels both shunt resistors \(R_1\), but they cannot be equal — the question fixes the input pole at 0.1 MHz with \(C_1=100\ \text{pF}\) and the output pole at 1 MHz with \(C_2=5\ \text{pF}\). They are treated below as \(R_1\) (input) and \(R_2\) (output) and are recovered from the two stated pole frequencies.

Approach. Recover the two node resistances from the stated poles, show why the uncompensated amplifier cannot be closed at unity gain, then use the exact two-node transfer function with \(C_f\) in place to size the capacitor so that the second pole sits about an octave above the unity-gain frequency.

  1. Recover the node resistances. Each pole is a simple RC at its own node: \[R_1=\frac{1}{2\pi f_{P1}C_1}=\frac{1}{2\pi(10^{5})(100\ \text{pF})}=15.92\ \text{k}\Omega,\qquad R_2=\frac{1}{2\pi f_{P2}C_2}=31.83\ \text{k}\Omega.\] The stage itself therefore has a gain \(g_mR_2=40\ \text{mA/V}\times 31.83\ \text{k}\Omega=1273\) (62.1 dB); the rest of the 100 dB comes from the input stage ahead of it, which is flat over the frequencies of interest.
  2. Show that the uncompensated amplifier is unusable at \(\beta=1\). Above 1 MHz the gain falls at 40 dB/decade, so unity gain is reached at \[f_{t}=\sqrt{A_0f_{P1}f_{P2}}=\sqrt{10^{5}(10^{5})(10^{6})}=100\ \text{MHz},\] \[\text{PM}=180^{\circ}-\arctan\frac{f_t}{f_{P1}}-\arctan\frac{f_t}{f_{P2}}=180^{\circ}-89.94^{\circ}-89.43^{\circ}=0.6^{\circ}.\] That is a ringing, effectively oscillatory closed loop. The supplied Bode plot says the same thing graphically: the amplifier is stable only for closed-loop gains of about 85 dB or more, which is no use for a general-purpose op amp.
  3. Write the exact transfer function with \(C_f\) in place. Two node equations at B and C give a second-order denominator \[D(s)=1+s\underbrace{\left[C_1R_1+C_2R_2+C_f\left(g_mR_1R_2+R_1+R_2\right)\right]}_{\textstyle b_1}+s^{2}\underbrace{R_1R_2\left[C_1C_2+C_f(C_1+C_2)\right]}_{\textstyle b_2},\] together with a right-half-plane zero at \(f_Z=g_m/2\pi C_f\) from the forward path through \(C_f\). For widely separated real poles \[f'_{P1}\simeq\frac{1}{2\pi b_1},\qquad f'_{P2}\simeq\frac{b_1}{2\pi b_2}.\] This is pole splitting: increasing \(C_f\) pushes the first pole down and the second pole up, towards the ceiling \(g_m/2\pi(C_1+C_2)=60.6\ \text{MHz}\).
  4. Choose the design criterion, and justify it. With one dominant pole the unity-gain frequency is \(f_t=A_0f'_{P1}\), and the phase margin at \(\beta=1\) is governed by how far the second pole sits above \(f_t\). Placing \(f'_{P2}=f_t\) gives only 45°, which rings; placing \(f'_{P2}=2f_t\) gives about 63°, close to the maximally flat closed-loop response and the usual industrial target. Imposing \(f_t=f'_{P2}/2\), that is \(b_1^{2}=2A_0b_2\), and solving for \(C_f\) gives 29.5 pF, so take the nearest standard value: \[\boxed{C_f=30\ \text{pF}}\] Justification: 30 pF is large enough to dominate \(C_1\) once multiplied by the Miller factor \(1+g_mR_2=1274\), so the input node alone sets the roll-off; it is small enough that the split-out second pole (52.6 MHz) stays a factor of two above the crossover; and it keeps the right-half-plane zero far away at 212 MHz.
  5. New pole locations. Evaluating \(b_1\) and \(b_2\) at \(C_f=30\ \text{pF}\): \[\boxed{f'_{P1}=260\ \text{Hz},\qquad f'_{P2}=52.6\ \text{MHz}}\] The Miller shortcut agrees: \(f'_{P1}\approx 1/2\pi R_1[C_1+C_f(1+g_mR_2)]=261\ \text{Hz}\), and factoring the exact quadratic gives 260.4 Hz and 52.60 MHz. The first pole has moved down by a factor of 384 while the second has moved up by a factor of 52.6 — the signature of pole splitting, and the reason a single small capacitor can do what a large shunt capacitor at node B could not.
  6. Unity-gain frequency and phase margin. \[f_t=A_0f'_{P1}=10^{5}\times 260.4\ \text{Hz}=26.0\ \text{MHz},\] \[\text{PM}=180^{\circ}-\arctan\frac{f_t}{f'_{P1}}-\arctan\frac{f_t}{f'_{P2}}=180^{\circ}-90.0^{\circ}-26.3^{\circ},\] \[\boxed{\text{PM}\approx 63.7^{\circ}\ \ (56.7^{\circ}\ \text{once the RHP zero at }212\ \text{MHz is included})}\] Either figure is a comfortable margin: the closed-loop step response overshoots only a few per cent, and the gain margin is set by the 40 dB/decade region well beyond 50 MHz. The 26 MHz gain–bandwidth product is the price paid, down from a nominal 100 MHz uncompensated, and that trade is the whole content of frequency compensation.
10¹10²10³10⁴10⁵10⁶10⁷10⁸10⁹f (Hz)020406080100120|A| (dB)uncompensatedcompensated260 Hzf t = 26 MHz52.6 MHz
Question 5. Asymptotic open-loop magnitude. Compensation drops the first pole from 0.1 MHz to 260 Hz and lifts the second from 1 MHz to 52.6 MHz, so unity gain is crossed on a clean -20 dB/decade slope.
ResultSymbolValue
Input / output node resistances\(R_1,\ R_2\)15.92 kΩ, 31.83 kΩ
Uncompensated unity-gain frequency and margin\(f_t\), PM100 MHz, \(0.6^{\circ}\) (unstable)
Compensation capacitor\(C_f\)30 pF
New first pole\(f'_{P1}\)260 Hz
New second pole\(f'_{P2}\)52.6 MHz
Right-half-plane zero\(f_Z\)212 MHz
New unity-gain frequency\(f_t\)26.0 MHz
New phase marginPM\(63.7^{\circ}\) (\(56.7^{\circ}\) with the RHP zero)
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