Question 6 of 7: Digital-to-Analog Conversion with a Zero-Order Hold

Question 6: Digital-to-Analog Conversion with a Zero-Order Hold (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Find. The analog voltage the converter puts out during the sampling interval that follows instant $t$.

Approach. Decode each register into the fraction of the reference voltage it represents by weighting bit $k$ with $2^{-k}$, multiply by the reference, and then apply the definition of a zero-order hold — the output is held at the most recent sampled value, so it is a constant across the interval.

1. State the converter output equation. In a weighted-resistor or ladder DAC each register bit switches in a current proportional to its place value, so with $B_1$ the most significant bit $$E_{\text{out}} = E_{\text{ref}} \sum_{k=1}^{n} B_k\,2^{-k},$$ that is $E_{\text{ref}}$ times $\left(0.5B_1 + 0.25B_2 + 0.125B_3 + 0.0625B_4 + 0.03125B_5 + 0.015625B_6\right)$, taking the output amplifier gain as unity, which is the standard convention unless a gain is stated.
2. Decode the register at instant $t$. The contents are 1 0 1 1 0 1, so the non-zero weights are those of $B_1$, $B_3$, $B_4$ and $B_6$: $$\sum B_k 2^{-k} = 0.5 + 0.125 + 0.0625 + 0.015625 = 0.703125 = \frac{45}{64}.$$
3. Convert that fraction to a voltage. $$E(t) = 10 \times 0.703125 = \boxed{E(t) = 7.03125\ \text{V.}}$$
4. Decode the previous instant, for the step size. At $t-1$ the register held 1 0 1 0 1 0, giving $0.5 + 0.125 + 0.03125 = 0.65625 = \tfrac{42}{64}$ and $E(t-1) = 6.5625$ V. The output therefore steps up by $$\Delta E = 7.03125 - 6.5625 = 0.46875\ \text{V}$$ at instant $t$ — three least-significant-bit counts, since the binary count moved from 42 to 45.
5. Apply the zero-order hold. A zero-order hold reconstructs a continuous signal by latching the most recent sample and holding it unchanged until the next one arrives; its output is a piecewise-constant staircase, and it uses no information about the rate of change. Hence for the whole interval $t \le \theta < t + \tau$, $$\boxed{E(\theta) = E(t) = 7.03125\ \text{V, constant for the full } 0.5\ \text{s interval.}}$$ The reading at $t-1$ therefore does not enter the answer; it is given so that the step, and the contrast with a first-order hold, can be seen.
6. Quote the resolution, which bounds the accuracy of that value. A six-bit register can express $2^{6} = 64$ levels, that is 63 steps between zero and full scale, so $$\text{resolution} = \frac{E_{\text{ref}}}{2^{n}-1} = \frac{10}{63} = 0.1587\ \text{V per count,}$$ and the largest output the converter can produce is $E_{\text{ref}}(1 - 2^{-6}) = 9.84375$ V, which falls short of the 10 V reference by exactly one least-significant-bit weight of 0.15625 V. Every held value therefore carries a quantisation uncertainty of about $\pm 0.079$ V.

For comparison, a first-order hold would extrapolate at the slope implied by the last two samples, $\alpha = \Delta E / \tau = 0.46875/0.5 = 0.9375$ V/s, ramping from 7.03125 V to 7.5 V across the interval. That tracks a smoothly varying signal more closely but overshoots badly at a reversal, which is why the zero-order hold is the standard output stage of an industrial DAC and why this question specifies it.

Final results.