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23-Mechatronics-A2 Circuits and Electronics: December 2018

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Bridge network — equivalent resistance, current, power
  2. Question 2 Superposition theorem
  3. Question 3 First-order RC switching transient
  4. Question 4 Thévenin equivalent with a dependent source, maximum power transfer
  5. Question 5 AC nodal analysis and power supplied by a source
  6. Question 6 Second-order RLC switching, Laplace-domain solution
  7. Question 7 Op-amp T-feedback network — output offset and small-signal gain
  8. Question 8 Full-wave diode-bridge rectifier with capacitive filter
  9. Question 9 Common-gate MOSFET amplifier — gain, input and output resistance
  10. Question 10 Enhancement-load NMOS inverter — voltage transfer characteristic
  11. Question 11 BJT bias-point analysis, five sub-circuits

Start with Question 1 →

Paper: National Exams, December 2018 — 16-Mex-A2 Circuits and Electronics. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Two parts: Part A — Circuits (Q1–Q6) and Part B — Electronics (Q7–Q11); candidates normally answer 5 of the 11 questions (3+2 or 2+3 split). Full worked solutions to all eleven questions are given below so the set can be used for study regardless of which five a candidate chose.

Reference texts: C. K. Alexander & M. N. O. Sadiku, Fundamentals of Electric Circuits (7th ed.) — resistive networks, superposition, Thévenin/max-power transfer, first-order and second-order transients, AC steady-state nodal analysis; W. H. Hayt et al., Engineering Circuit Analysis (9th ed.) — Laplace-domain circuit models; A. S. Sedra & K. C. Smith, Microelectronic Circuits (8th ed.) — op-amp T-network feedback, diode rectifiers, MOSFET common-gate stages, NMOS inverters, and BJT bias-point analysis.

Reading the figures. The paper supplies the schematics but no separate figure data; every network below is redrawn element-by-element directly from the original drawing (several figures are small hand-style schematics). All node/reference choices and source polarities are stated with the solution. Q11 uses printed variable names (e.g. “VE”) exactly as labelled on the original circuit, even where the labelled terminal is physically the collector in one sub-part — this is called out explicitly where it occurs.