23-Mechatronics-A2 Circuits and Electronics · December 2018
Question 9 of 11: Common-gate MOSFET amplifier — gain, input and output resistance
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper: National Exams, December 2018 — 16-Mex-A2 Circuits and Electronics. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Two parts: Part A — Circuits (Q1–Q6) and Part B — Electronics (Q7–Q11); candidates normally answer 5 of the 11 questions (3+2 or 2+3 split). Full worked solutions to all eleven questions are given below so the set can be used for study regardless of which five a candidate chose.
Reference texts: C. K. Alexander & M. N. O. Sadiku, Fundamentals of Electric Circuits (7th ed.) — resistive networks, superposition, Thévenin/max-power transfer, first-order and second-order transients, AC steady-state nodal analysis; W. H. Hayt et al., Engineering Circuit Analysis (9th ed.) — Laplace-domain circuit models; A. S. Sedra & K. C. Smith, Microelectronic Circuits (8th ed.) — op-amp T-network feedback, diode rectifiers, MOSFET common-gate stages, NMOS inverters, and BJT bias-point analysis.
Reading the figures. The paper supplies the schematics but no separate figure data; every network below is redrawn element-by-element directly from the original drawing (several figures are small hand-style schematics). All node/reference choices and source polarities are stated with the solution. Q11 uses printed variable names (e.g. “VE”) exactly as labelled on the original circuit, even where the labelled terminal is physically the collector in one sub-part — this is called out explicitly where it occurs.
Question 9: Common-gate MOSFET amplifier — gain, input and output resistance [12, 4, 4]
Figure-9: common-gate NMOS amplifier. $R_1$/$R_2$ set the (ac-grounded) gate bias; input $v_{in}$ applied at the source through $C_1$; output taken at the drain through $C_2$ across $R_D$.
Approach. Find the small-signal parameters $g_m$, $r_o$ from the fixed bias current, then solve the two-node ($v_d$, $v_s$) small-signal circuit of the common-gate stage (gate at ac ground) including $r_o$ exactly rather than the $g_m R_D$ shortcut, since $r_o$ is not negligible here.
Small-signal parameters. With $I_D=I_{bias}=2\ \text{mA}$ fixed by the tail source, $$g_m=\sqrt{2KI_D}=\sqrt{2\times1\times2}=2\ \text{mA/V},\qquad r_o=\frac{1}{\lambda I_D}=\frac{1}{0.1\times2\,\text{mA}}=5\ \text{k}\Omega.$$
Small-signal model. Gate is ac ground ($v_g=0$), so $v_{gs}=-v_s$. The dependent current source $g_mv_{gs}=-g_mv_s$ and $r_o$ both connect drain node $d$ to source node $s$; $R_D$ connects $d$ to ac ground; the test/input excitation connects to $s$.
Node equations. With a unit test current $I_{in}=1\,\text{A}$ injected at the source node: $$v_d\Big(\frac1{R_D}+\frac1{r_o}\Big)=v_s\Big(\frac1{r_o}+g_m\Big),\qquad -\frac{v_d}{r_o}+v_s\Big(\frac1{r_o}+g_m\Big)=I_{in}.$$ Solving numerically gives $v_s=636.4$, $v_d=2000$ (per amp of test current).
Small-signal gain. With $v_{in}=v_s$ (ideal source, no series resistance) and $v_o=v_d$: $$\frac{v_o}{v_{in}}=\frac{v_d}{v_s}=\boxed{3.14}.$$ (Equivalently, the exact common-gate formula $A_v=\dfrac{(1+g_mr_o)R_D}{r_o+R_D}=\dfrac{(1+10)\times2}{7}=3.14$.)
Output resistance. Looking into the drain with the ideal source driving $v_s$ directly (zero source impedance), $r_o$ appears simply in parallel with $R_D$: $$R_o=R_D\|r_o=\frac{2\times5}{7}=\boxed{1.429\ \text{k}\Omega}.$$