Question 10 of 11: Enhancement-load NMOS inverter — voltage transfer characteristic

Question 10: Enhancement-load NMOS inverter — voltage transfer characteristic [12, 2, 2, 2, 2]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

$M_2$ is the load, wired diode-connected ($V_{GS2}=V_{DD}-v_{OUT}$, always driven by its own drain current) with its source at $v_{OUT}$ and drain at $+V_{DD}$; $M_1$ is the driver, gate at $v_{IN}$, source grounded, drain at $v_{OUT}$. No numeric $V_{DD}$ or $V_{TN}$ is given, so every breakpoint below is expressed symbolically in terms of $V_{DD}$ and the common threshold $V_{TN}$.

Region A — $v_{IN} $M_1$ carries no current, so $M_2$ (diode-connected, always needing $I_{D2}=0$ here too since the two are in series) also carries none; with zero drain current, $M_2$’s $V_{GS2}=V_{TN}$ exactly, giving the highest output the inverter can reach: $$V_{OH}=V_{DD}-V_{TN}$$ (an enhancement diode-connected load, unlike a resistor pull-up, can never lift $v_{OUT}$ all the way to $V_{DD}$).

Region B — both transistors in saturation. As $v_{IN}$ rises just past $V_{TN}$, $M_1$ turns on in saturation while $M_2$ (diode-connected) is always in saturation whenever it conducts (its own $V_{DS2}=V_{GS2}>V_{GS2}-V_{TN}$ is automatic). Equal $K$ for identical devices and equal drain current through both (they are in series) gives $V_{GS1}-V_{TN}=V_{GS2}-V_{TN}$, i.e. a very steep transition — the hallmark of an enhancement-load inverter’s narrow, near-vertical switching region. The switching threshold $V_M$ (where $v_{IN}=v_{OUT}$, a convenient reference point) satisfies $K(V_M-V_{TN})^2=K(V_{DD}-V_M-V_{TN})^2\Rightarrow V_M=\dfrac{V_{DD}}{2}$ for identical devices.

Region C — $M_1$ in triode, $M_2$ in saturation. Once $v_{IN}$ is well above $V_{TN}$, $M_1$ is pulled into the triode region and $v_{OUT}$ drops toward its logic-low value; $M_2$ remains saturated (diode-connected devices are saturated whenever $I_{D2}>0$). $V_{OL}$ is the (small, non-zero) drain-source drop across $M_1$ in deep triode carrying the fixed current set by $M_2$’s saturation equation — it approaches, but never reaches, zero.

Noise margins. With the standard unity-slope ($dv_{OUT}/dv_{IN}=-1$) definitions of $V_{IL}$ and $V_{IH}$ (found on either side of the steep Region-B transition): $$NM_L=V_{IL}-V_{OL},\qquad NM_H=V_{OH}-V_{IH}.$$ Because the transition region is very narrow for an enhancement-load inverter (both devices have the same $K$, so the region-B slope is steep), $V_{IL}$ and $V_{IH}$ sit close together near $V_M=V_{DD}/2$, which tends to make $NM_L$ larger and $NM_H$ smaller than in a comparable resistor-load design — the load never reaching $V_{DD}$ caps $V_{OH}$ below the supply rail and directly narrows $NM_H$.