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17-Phys-A5: May 2018

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 BJT Current-Mirror Bias Network
  2. Question 2 Active Filter — Inverting Amplifier Cascaded with a Passive High-Pass Stage
  3. Question 3 Common-Source PMOS Amplifier with Diode-Connected Load
  4. Question 4 Series-Shunt (Voltage-Series) Feedback Amplifier
  5. Question 5 Weighted-Resistor (Binary-Ladder) Digital-to-Analog Converter
  6. Question 6 CMOS Logic Gate — Pull-Down Network by PUN/PDN Duality

Start with Question 1 →

17-Phys-A5-B, Analog and Digital Electronic Circuits — National Exams, May 2018. 6 questions, marks as shown in the paper's marking scheme (Q1: 15; Q2: 10+10; Q3: 10+10; Q4: 15; Q5: 5+10; Q6: 10+5). Open-book exam; any non-communicating calculator permitted.

Reference texts: A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. (Sedra-Smith) — used throughout for BJT/MOSFET biasing, current mirrors, op-amp and feedback-amplifier analysis. M. M. Mano and M. D. Ciletti, Digital Design, 6th ed. (Mano-Digital) — used for the CMOS pull-up/pull-down duality construction in Question 6.