Common-Source PMOS Amplifier with Diode-Connected Load: 17-Phys-A5, May 2018, Q3

Question 3: Common-Source PMOS Amplifier with Diode-Connected Load (10+10 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. $M_1$ (PMOS, common source, gate driven by an ideal source $v_{sig}$) drives the output node $v_o$, loaded by $M_2$ (NMOS current source, gate on the $M_b$ mirror rail) and $M_3$ (NMOS, diode-connected: gate tied to its own drain at $v_o$) and $C_L$. $I_{bias}=1\text{mA}$ sets $M_b$'s (and hence $M_2$'s) current via the mirror; $I_{D3}=1\text{mA}$ is given directly. All $r_o=\infty$.

Symbol	Value
$(W/L)_1=(W/L)_2$	$4$
$(W/L)_b$	$40$
$(W/L)_3$	$80$
$\mu_nC_{ox}=\mu_pC_{ox}$	$100\ \mu\text{A/V}^2$
$I_{bias}$, $I_{D3}$	$1\text{mA}$ each
$C_L$, $C_{gs}$, $C_{gd}$	$50\text{fF}$, $50\text{fF}$, $20\text{fF}$

Find. (a) $A_v=v_o/v_{sig}$. (b) $f_{3\text{dB}}$.

[Figure not reproduced: Fig. 3 as printed in the source paper. See the official exam paper or the cited reference text.]

Fig. 3 — $M_b$ (diode-connected) mirrors $I_{bias}$ into $M_2$; $M_3$ is diode-connected at the output node, setting the finite load resistance $1/g_{m3}$ that $M_1$'s infinite-$r_o$ drain current develops into.

Approach. Find the DC bias currents from the mirror ratio and node KCL, compute $g_{m1}$ and $g_{m3}$, then use $A_v=-g_{m1}R_{out}$ with $R_{out}=1/g_{m3}$ (the only finite resistance at the output, since every $r_o=\infty$); for the bandwidth, form the single dominant pole at the output node from $R_{out}$ and the total node capacitance.

Mirror current into $M_2$. $$I_{D2}=I_{bias}\cdot\frac{(W/L)_2}{(W/L)_b}=1\text{mA}\times\frac{4}{40}=0.100\text{ mA}.$$
DC current through $M_1$, by KCL at $v_o$. $M_1$'s drain current supplies both $M_2$'s sink current and $M_3$'s diode current: $$I_{D1}=I_{D2}+I_{D3}=0.100+1.000=1.100\text{ mA}.$$
Transconductances. $$g_{m1}=\sqrt{2\mu_pC_{ox}(W/L)_1 I_{D1}}=\sqrt{2(100\mu)(4)(1.1\text{m})}=0.938\text{ mA/V},$$ $$g_{m3}=\sqrt{2\mu_nC_{ox}(W/L)_3 I_{D3}}=\sqrt{2(100\mu)(80)(1\text{m})}=4.00\text{ mA/V}.$$
Low-frequency gain. With $r_{o1}=r_{o2}=\infty$, the only finite output resistance is $M_3$'s diode connection, $R_{out}=1/g_{m3}$: $$\boxed{A_v=-g_{m1}R_{out}=-\frac{g_{m1}}{g_{m3}}=-\frac{0.938}{4.00}=-0.235\text{ V/V}\ (-12.6\text{ dB})}.$$
(b) Total capacitance at the output node. With $v_{sig}$ an ideal source (zero $R_{sig}$), the pole is set entirely by $R_{out}$ and the node's own capacitance: $C_L$ (given), $C_{gd1}$ (bridges $v_o$ to the ideal-source gate, so it loads $v_o$ fully once the source is zeroed for the resistance calculation), $C_{gd2}$ ($M_2$'s gate sits on the AC-grounded mirror-bias node), and $C_{gs3}$ (from $M_3$'s gate, which IS $v_o$, to its grounded source) — $C_{gd3}$ has both plates at $v_o$ and contributes nothing. $$C_{tot}=C_L+C_{gd1}+C_{gd2}+C_{gs3}=50+20+20+50=140\text{ fF}.$$
3-dB frequency. $$R_{out}=\frac{1}{g_{m3}}=250\ \Omega,\qquad \boxed{f_{3\text{dB}}=\frac{1}{2\pi R_{out}C_{tot}}=\frac{1}{2\pi(250)(140\text{fF})}=4.55\text{ GHz}}.$$ This is the standard dominant-pole answer the question expects.
Check: the $C_{gd1}$ feedforward zero. Because $v_{sig}$ is ideal, $C_{gd1}$ also couples the input straight to $v_o$, so the exact transfer function is $$\frac{v_o}{v_{sig}}(s)=-\frac{g_{m1}-sC_{gd1}}{g_{m3}+sC_{tot}},$$ with a right-half-plane zero at $g_{m1}/(2\pi C_{gd1})=7.47\text{ GHz}$, only 1.64 times the pole. The rising zero magnitude partly cancels the pole’s roll-off, so $|v_o/v_{sig}|$ actually falls to $0.707$ of its DC value at about $8.95\text{ GHz}$. Quote $4.55\text{ GHz}$ as the pole-limited bandwidth; it is a conservative estimate of the true −3 dB point.

Final results
Quantity	Result
$I_{D1}$	$1.10\text{ mA}$
$g_{m1}$	$0.938\text{ mA/V}$
$g_{m3}$	$4.00\text{ mA/V}$
$A_v=v_o/v_{sig}$	$-0.235\text{ V/V}$ ($-12.6\text{ dB}$)
$R_{out}$	$250\ \Omega$
$C_{tot}$	$140\text{ fF}$
$f_{3\text{dB}}$ (dominant pole)	$4.55\text{ GHz}$
Exact −3 dB point with the $C_{gd1}$ zero	$\approx 8.95\text{ GHz}$

Topic: Common-source amplifier with a diode-connected load and infinite-$r_o$ devices.

Key relations: Square-law $g_m=\sqrt{2k'(W/L)I_D}$; diode-connected MOSFET small-signal resistance $=1/g_m$ (when $r_o=\infty$); single-pole bandwidth $f_{3\text{dB}}=1/(2\pi R_{out}C_{tot})$.

Why this works: With every transistor's Early voltage infinite, $M_1$ and $M_2$ contribute zero output conductance — without $M_3$'s diode connection the node would have no DC operating point or finite gain at all. Diode-connecting $M_3$ deliberately trades a high (infinite) load resistance for a well-defined, finite one, which is the standard way to build an amplifier stage with infinite-$r_o$ devices when a fully cascoded current-source load isn't used.

Common pitfall: Counting $C_{gd3}$ as loading the output — since $M_3$'s gate and drain are the SAME node ($v_o$), that capacitor has zero voltage across it and stores no signal charge; only $C_{gs3}$ (gate-to-grounded-source) loads the node. Also easy to miss: $C_{gd1}$ still loads $v_o$ fully even though it's driven by an "ideal source," because the resistance/pole calculation zeroes independent sources, turning $v_{sig}$'s node into an AC ground.

Source: Sedra-Smith §7.3 (Small-Signal Operation), §9.2 (High-Frequency Response of the CS Amplifier), Ch.6 current mirrors.

Question 3 of 6: Common-Source PMOS Amplifier with Diode-Connected Load

Question 3: Common-Source PMOS Amplifier with Diode-Connected Load (10+10 marks)