CMOS Logic Gate — Pull-Down Network by PUN/PDN Duality: 17-Phys-A5, May 2018, Q6

Question 6: CMOS Logic Gate — Pull-Down Network by PUN/PDN Duality (10+5 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. PUN (all PMOS) between $V_{DD}$ and $Y$: a top block of $C$ and $D$ in parallel, in series with a bottom block of $A$ in parallel with ($B$ in series with $C$).

Find. (a) The dual PDN and the complete CMOS gate. (b) The Boolean function $Y(A,B,C,D)$.

Fig. 6 (given) — PUN: $(C\Vert D)$ in series with $\big(A\Vert(B\text{ series }C)\big)$, all PMOS.

Approach. Apply the standard CMOS duality construction — replace every PMOS by an NMOS on the SAME gate signal, and swap every series connection for parallel and every parallel connection for series — then read the switch-conduction function directly from the PUN (PMOS closes when its gate input is 0) to get $Y$.

Dualize each block. Series $\leftrightarrow$ parallel, same gate labels, PMOS $\to$ NMOS: the top block $(C\Vert D)$ becomes $(C\text{ series }D)$; the bottom block $\big(A\Vert(B\text{ series }C)\big)$ becomes $\big(A\text{ series }(B\Vert C)\big)$.
Dualize the outer connection. The two blocks are in SERIES in the PUN, so in the PDN they go in PARALLEL: $$\text{PDN}=(C\cdot D)\ \Vert\ \big(A\cdot(B\Vert C)\big),\quad\text{all NMOS, gates }A,B,C,D.$$
Complete CMOS gate. The PDN (Fig. 6b) sits between $Y$ and ground, with the given PUN unchanged between $V_{DD}$ and $Y$ — every input drives one PMOS in the PUN and one NMOS in the PDN, satisfying the standard CMOS complementary-network requirement (exactly one of PUN/PDN conducts for any input combination).
(b) Boolean function, from the PUN switch model. A PMOS switch closes when its input is 0, so writing each block's "closed" condition directly: $$T_{top}=\bar C+\bar D,\qquad T_{bot}=\bar A+\bar B\bar C,\qquad Y=T_{top}\cdot T_{bot}=(\bar C+\bar D)(\bar A+\bar B\bar C).$$ Expanding and dropping the term absorbed by $\bar B\bar C$ (since $\bar B\bar C+\bar B\bar C\bar D=\bar B\bar C$): $$\boxed{Y=\bar A\bar C+\bar B\bar C+\bar A\bar D = \bar C(\bar A+\bar B)+\bar A\bar D}.$$

Fig. 6b (derived) — PDN: $(C\cdot D)$ in parallel with $\big(A\cdot(B\Vert C)\big)$, all NMOS on the same four gate signals as the given PUN.

Final results
Quantity	Result
PDN topology	$(C\cdot D)\ \Vert\ \big(A\cdot(B\Vert C)\big)$, NMOS
Boolean function $Y$	$\bar A\bar C+\bar B\bar C+\bar A\bar D$

Check

The PUN conduction function, the simplified SOP above, and the PDN-vs-$\overline{Y}$ duality were all cross-checked against the full 16-row truth table (exhaustive, not spot-checked) — zero mismatches.

Topic: CMOS complementary pull-up/pull-down network duality.

Key relations: PUN series $\leftrightarrow$ PDN parallel (and vice versa) on the same gate signals; PMOS conducts on input$=0$, NMOS conducts on input$=1$; complementary CMOS requires PDN $=\overline{\text{PUN}}$ (exactly one network conducts for every input combination, so the output is always driven, never floating).

Why this works: A series connection of switches conducts only when ALL are closed (an AND of "closed" conditions), while a parallel connection conducts when ANY is closed (an OR); De Morgan's theorem is exactly what turns an AND-of-PMOS-closed-conditions into an OR-of-NMOS-closed-conditions when every literal is complemented by switching device type, which is precisely the series$\leftrightarrow$parallel swap.

Common pitfall: Complementing the gate LABELS when building the PDN (writing $\bar A,\bar B,\bar C,\bar D$ on the NMOS gates) — the labels stay the same; only the device type (NMOS instead of PMOS) and the series/parallel structure change, because it is the transistor's own conduction condition that flips, not the input signal.

Source: Mano-Digital §10.5–10.6 (CMOS logic gates, complementary networks).

Question 6 of 6: CMOS Logic Gate — Pull-Down Network by PUN/PDN Duality

Question 6: CMOS Logic Gate — Pull-Down Network by PUN/PDN Duality (10+5 marks)