Question 1 of 5: 220-Space Parking Garage Counter

Question 1: 220-Space Parking Garage Counter (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Garage capacity 220 spaces, 1 entrance sensor (count-up pulse), 2 exit sensors (either produces a count-down pulse), FULL sign + entrance-gate solenoid to drive.

Find. (a) A counter + comparator circuit that asserts FULL exactly when the occupied count reaches 220, gates off further entrance counting while full, and always allows exit counting; (b) a description of its operation.

Approach. Pick the smallest standard up/down counter width that can hold 220, cascade enough 74193s to reach it, decode the target count with a comparator, and interlock the comparator's output back onto the entrance clock so the count can never be driven past 220.

1. Part (a) — size the counter. A single 74193 is a 4-bit up/down counter (range 0–15), too small. Two bits are the smallest binary word that can hold 220: $2^7-1=127 < 220 \le 2^8-1=255$, so an 8-bit counter (two cascaded 74193s) is the minimum standard size, giving range 0–255.
2. Cascade the counters. Wire the low-nibble 74193's terminal count-up output $TC_U$ to the high-nibble's count-up clock $CP_U$ (and likewise $TC_D\to CP_D$ for borrow on the down side), so the pair behaves as one 8-bit up/down counter $Q_7\ldots Q_0$. The entrance sensor pulse drives $CP_U$ of the low nibble (through the interlock AND gate, next step); the OR of the two exit sensors drives $CP_D$ of the low nibble directly — either exit is always allowed to decrement, even while FULL is asserted, so the count self-corrects the instant a car leaves.
3. Decode FULL. $220_{10} = 11011100_2$. An 8-bit magnitude comparator (e.g. 74LS85, or the AND/OR bit-decode of $Q_7Q_6\overline{Q_5}Q_4Q_3\overline{Q_2Q_1Q_0}$) compares $Q_7\ldots Q_0$ against the hard-wired constant $11011100$ and asserts $\text{FULL}=1$ exactly on an exact match.
4. Interlock the entrance clock. The entrance sensor pulse is ANDed with $\overline{\text{FULL}}$ before reaching $CP_U$, so once the count reaches 220 no further up-pulses are accepted — the counter physically cannot overshoot. FULL directly drives the FULL sign and the entrance-gate solenoid.
5. Part (b) — operation. Every entrance pulse increments the 8-bit counter by one, provided FULL is not already asserted; every exit pulse (from either gate, ORed onto the shared down-clock) decrements it by one unconditionally. The comparator continuously watches the counter outputs against the binary pattern for 220. The instant the count reaches 220 the comparator's output goes HIGH, which lights the FULL sign, drops the entrance gate bar, and simultaneously blocks the AND gate feeding $CP_U$ so no further vehicle can be counted in. As soon as any vehicle exits, the down-clock decrements the count to 219, the comparator output drops LOW, the FULL sign extinguishes, the entrance gate reopens, and the AND gate re-admits entrance pulses. No separate latch is needed because the comparator's match condition is itself instantaneously true only at exactly 220 — a purely combinational, self-clearing FULL signal.