Question 3 of 5: BCD-to-Braille Converter

Question 3: BCD-to-Braille Converter (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The 10 Braille dot patterns for digits 0–9 (read directly from the printed figure), each digit input as a 4-bit BCD code $B_3B_2B_1B_0$ (0000–1001); codes 1010–1111 never occur (invalid BCD).

[Figure not reproduced: Figure Q3 (redrawn to scale): the 2×2 Braille dot cell (W top-left, X top-right, Y bottom-left, Z bottom-right) for each digit 0–9. See the official exam paper.]

Find. (a) Minimized SOP for $W,X,Y,Z$ as functions of $B_3B_2B_1B_0$, treating codes 10–15 as don't-cares; (b) $Y$ built from 2-input NOR gates only; (c) $W$ with a minimum gate count.

Approach. Map each dot to its 1-set over the 10 valid BCD codes, take the unused codes 10–15 as don't-cares, minimize each output by Karnaugh map / Quine–McCluskey, then realize $Y$ purely with 2-input NOR gates via De Morgan bubble-pushing and $W$ with the fewest gates by spotting its XOR structure.

1. Part (a) — minimize each output. Grouping the K-maps for each dot (don't-cares 10–15 used freely) gives $$\boxed{W = B_1 + B_2 + (B_3\oplus B_0)}\ \big(=B_1+B_2+B_3\overline{B_0}+\overline{B_3}B_0\big),$$ $$X = B_0B_1 + B_0B_3 + B_2\overline{B_0} + \overline{B_0}\,\overline{B_1}\,\overline{B_3},$$ $$Y = B_3 + B_1B_2 + \overline{B_0}\,\overline{B_2}, \qquad Z = B_0B_2 + \overline{B_0}\,\overline{B_1}.$$
2. List assumptions. (i) Codes $1010_2$–$1111_2$ never occur at the input (standard BCD assumption) and are treated as don't-cares in the minimization; (ii) the dot cell is read top-left$\to$W, top-right$\to$X, bottom-left$\to$Y, bottom-right$\to$Z, per the figure's own key; (iii) "active-HIGH" means a raised dot corresponds to output $=1$, matching the truth table given in the figure.
3. Part (b) — realize $Y$ with 2-input NOR only. Two standard identities make this possible without first building full inverters everywhere: $A+B=\text{NOR}(\text{NOR}(A,B),\text{NOR}(A,B))$ (a NOR followed by a NOR-as-inverter), and $\overline{A}\,\overline{B}=\text{NOR}(A,B)$ directly (no inverters needed at all). Since $Y=B_3+(B_1B_2)+(\overline{B_0}\,\overline{B_2})$: the term $\overline{B_0}\,\overline{B_2}=\text{NOR}(B_0,B_2)$ costs one gate; the term $B_1B_2=\text{NOR}(\overline{B_1},\overline{B_2})$ needs $\overline{B_1}=\text{NOR}(B_1,B_1)$ and $\overline{B_2}=\text{NOR}(B_2,B_2)$ first (2 gates) then the NOR itself (1 gate) — 3 gates; then the 3-way OR of $B_3$, that AND term, and that other AND term costs 4 more NOR gates (combine-then-invert, twice).

4. Part (c) — $W$ with minimum gates. Written as $W=B_1+B_2+B_3\overline{B_0}+\overline{B_3}B_0$, the last two terms are exactly the definition of $B_3\oplus B_0$. Recognizing that collapses four product terms into a single XOR: $\boxed{W = B_1 \text{ OR } B_2 \text{ OR } (B_3\oplus B_0)}$, realizable in just 3 gates — one 2-input XOR gate for $B_3\oplus B_0$ and two 2-input OR gates cascading $B_1$, $B_2$, and the XOR output — versus 2 AND gates + a 4-input OR (plus 2 inverters) for the literal SOP. Bit-identical to the part-(a) expression for $W$ over all 16 combinations.