Question 2 of 5: 3-Bit Gray Code and Gray-to-BCD Conversion

Question 2: 3-Bit Gray Code and Gray-to-BCD Conversion (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A 3-bit Gray-coded input $G_2G_1G_0$ representing the decimal digits 0–7; a PAL16L8 (AND-OR array) available for part (b); a 3-to-8 decoder (74LS138, active-LOW outputs) available for part (c).

Find. (a) The Gray-code definition and an advantage; (b) SOP equations for the BCD output bits realizable in a PAL's AND-OR array; (c) the same conversion built from a 3-to-8 decoder with a minimum gate count.

Approach. A 3-bit reflected binary Gray code only ever changes one bit between adjacent counts; convert it to binary/BCD with the standard ripple-XOR rule, then re-express that rule as a pure sum-of-products for the AND-OR-only PAL, and finally as decoder-minterm NAND combining for part (c).

1. Part (a) — definition and advantage. A 3-bit Gray code is a sequence of the eight 3-bit patterns $000,001,011,010,110,111,101,100$ (for decimal 0–7) chosen so that any two numerically adjacent codes differ in exactly one bit position — i.e. $G(n) = n \oplus (n\gg1)$. The key advantage: in a mechanical or optical position encoder, several output bits can never be guaranteed to change at exactly the same instant; with ordinary binary, a transition like $011\to100$ can pass through spurious intermediate codes ($010,110,\dots$) if bits don't switch simultaneously, giving a false reading. Because only one bit ever changes at a time in Gray code, the worst a timing skew can do is read the code one step early or late — never a wildly wrong value.
2. Part (b) — derive the SOP equations. The standard Gray-to-binary rule is $B_2=G_2$, $B_1=G_2\oplus G_1$, $B_0=G_2\oplus G_1\oplus G_0$. A PAL's AND-OR array has no native XOR gate, so each XOR is expanded to its own sum-of-products before it can be programmed: $$B_2 = G_2, \qquad B_1 = G_2\overline{G_1} + \overline{G_2}G_1,$$ $$\boxed{B_0 = \overline{G_2}\,\overline{G_1}G_0 + \overline{G_2}G_1\overline{G_0} + G_2\overline{G_1}\,\overline{G_0} + G_2G_1G_0}$$ — the 3-input-XOR SOP has no smaller cover (its four minterms are exactly the odd-parity rows), so all four product terms are needed. Since only 3-digit values 0–7 occur, the BCD digit's top bit $D_3=0$ always; $D_2D_1D_0=B_2B_1B_0$.

3. Part (c) — decoder + minimum gates. A 3-to-8 decoder (74LS138) with active-LOW outputs $\overline{Y_0}\ldots\overline{Y_7}$ asserts exactly one $\overline{Y_i}=0$ for input $=i$. Any sum-of-minterms function $F=\sum m(i,j,k,\ldots)$ is then built with a single NAND gate: $F=\text{NAND}(\overline{Y_i},\overline{Y_j},\overline{Y_k},\ldots)$, because $\text{NAND}$ of active-LOW lines is $1$ unless the input line is currently the active (LOW) one, i.e. exactly the OR semantics we want. Reading the minterm sets straight off the truth table used in step 2 ($B_2\!=\!1$ on $\{4,5,6,7\}$, $B_1\!=\!1$ on $\{2,3,4,5\}$, $B_0\!=\!1$ on $\{1,2,4,7\}$) gives $$B_2=\text{NAND}(\overline{Y_4},\overline{Y_5},\overline{Y_6},\overline{Y_7}),\ \ B_1=\text{NAND}(\overline{Y_2},\overline{Y_3},\overline{Y_4},\overline{Y_5}),\ \ B_0=\text{NAND}(\overline{Y_1},\overline{Y_2},\overline{Y_4},\overline{Y_7})$$ — three 4-input NAND gates total (plus the single decoder IC), the minimum possible since each output needs its own gate and none of the three minterm sets is a subset of another.