Flip-Flop Conversion, Frequency Divider, Shift-Register Simulation: 04-BS-8, December 2015, Q5

Question 5: Flip-Flop Conversion, Frequency Divider, Shift-Register Simulation (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Part (a): a T flip-flop (toggles when $T{=}1$) plus basic gates. Part (b): a 16 MHz, 20%-duty clock and an edge-triggered S-R flip-flop. Part (c): the circuit of Figure Q5 — an 8-bit shift register (serial input left, serial output right), an XOR gate feeding the serial output and the J-K's $Q$ back into serial input, and the J-K's $J=\text{OR}(\text{serial output}, \text{serial output})=\text{serial output}$, $K=\overline{J}$ (bubble on K) — i.e. the J-K is wired as a D flip-flop with $D=$ serial output, clocked by the same CLOCK; initial register $=01101010_2$ (MSB/left to LSB/right), J-K cleared ($Q{=}0$).

Find. (a) The T-to-JK conversion logic; (b) the SR-based divide-by-2 circuit; (c) the 8-bit register content after 8 clock pulses.

Approach. (a) Derive the excitation $T=f(J,K,Q)$ that reproduces the JK characteristic table, then wire it into a T flip-flop. (b) Use the well-known trick that an edge-triggered toggle stage (built from the SR flip-flop's own complementary outputs fed back to its inputs) always halves frequency to an exact 50% duty cycle, regardless of the input duty cycle. (c) Simulate the given feedback network cycle-by-cycle in Python.

Part (a) — derive $T$ from the JK characteristic table. The T flip-flop toggles exactly when $Q^{+}\ne Q$. Tabulating $Q^+\oplus Q$ over all 8 $(J,K,Q)$ combinations of the standard JK table and reading off the rows where a toggle is required gives $\boxed{T = J\overline{Q} + KQ}$. Build: a 2-input AND gate forms $J\overline{Q}$ (using the T flip-flop's own complementary $\overline{Q}$ output, fed back), a second AND gate forms $KQ$ (using the fed-back $Q$), and a 2-input OR gate combines them to drive the T flip-flop's toggle input.

JK-from-T: $T=J\overline{Q}+KQ$, using the T flip-flop's own $Q,\overline{Q}$ outputs fed back into the excitation logic.

Part (b) — SR self-toggle divider. Wiring an edge-triggered S-R flip-flop with $S=\overline{Q}$ and $R=Q$ (both fed back from its own outputs) makes it toggle on every active CLOCK edge: at each edge, $S{=}1,R{=}0$ sets $Q$ to 1 whenever $Q$ was 0, and $S{=}0,R{=}1$ resets $Q$ to 0 whenever $Q$ was 1 — a pure toggle, regardless of how long the clock spends HIGH vs. LOW within each period. Because the toggle only cares about the rising-edge instants, the output stays HIGH for exactly one full 16 MHz period and LOW for exactly one full 16 MHz period, so $f_{out}=f_{in}/2=8\text{ MHz}$ (verified: $16\text{ MHz}/2=8\text{ MHz}$) and the output duty cycle is forced to exactly $T_{in}/T_{out}=50\%$ — independent of the input's own 20% duty cycle.

SR self-toggle frequency divider and its waveforms: the 20%-duty 16 MHz input is halved to an exactly 50%-duty 8 MHz output, because only the rising-edge timing (not the duty cycle) of the input matters to a toggle stage.

Part (c) — simulate the feedback shift register. Let $s(t)$ be the register's current serial (rightmost) output and $q(t)$ the J-K/D flip-flop's current $Q$, cleared to 0. At every clock edge: the new bit shifted into the register's left end is $\text{newbit}=s(t)\oplus q(t)$ (the XOR feedback), the register shifts right by one position (discarding the old rightmost bit, which was just consumed by the XOR), and the D-wired J-K samples $q(t{+}1)=s(t)$. Working this through by hand for 8 pulses from the initial load $01101010$ gives:

Pulse	Register content
0 (initial)	01101010
1	00110101
2	10011010
3	11001101
4	11100110
5	11110011
6	11111001
7	01111100
8	10111110

Check

Assumes the register shifts left-to-right (new bit enters at the "Serial input" end shown on the figure's left, old bits move toward "Serial output" on the right, and the rightmost bit is discarded each shift) and that "loaded with $(01101010)_2$" lists the bits MSB(left)-to-LSB(right) in that same left-to-right sense — the natural reading of the figure and the stated bit string together, with no other convention stated in the source.

Quantity	Result
(a) T-to-JK excitation	$T=J\overline{Q}+KQ$
(b) Output frequency / duty	8 MHz, 50% (input 16 MHz, 20%)
(c) Register after 8 pulses	$\boxed{10111110_2}$

Concept & Theory

Topic. Flip-flop type conversion, edge-triggered frequency division, and simulating a shift register with combinational feedback.

Key relations. JK characteristic table and its toggle-condition decomposition; toggle-flip-flop frequency division ($f_{out}=f_{in}/2$, duty forced to 50%); D-type conversion of a JK flip-flop ($J{=}D,\ K{=}\overline{D}$), used inside the Q5(c) circuit itself.

Why this works. Any flip-flop type can be converted to any other by matching characteristic tables and solving for the needed excitation as a Boolean function of the target's own present state — the same technique used in (a) for T$\to$JK and, self-referentially, inside the given Q5(c) circuit for JK$\to$D. A toggle stage always yields exactly 50% output duty because only its two edge instants per input period matter, not how long the input spends high vs. low between them.

Common pitfall. Assuming duty-cycle information from the input carries through a toggle divider (it doesn't — the divider is a clean 50% regardless); or, in part (c), shifting the wrong direction / discarding the wrong end bit, which silently produces a different final pattern.

Source. Mano & Ciletti, Digital Design, Ch. 5 (flip-flop conversion, characteristic/excitation tables) & Ch. 6 (shift registers).

Question 5 of 5: Flip-Flop Conversion, Frequency Divider, Shift-Register Simulation

Question 5: Flip-Flop Conversion, Frequency Divider, Shift-Register Simulation (25 marks)