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04-BS-8: December 2019

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Synchronous Up-Down Counter (Non-Binary Sequences)
  2. Question 2 Boolean Minimization — POS/NOR, SOP/AND-OR, and NAND-Only Realizations
  3. Question 3 D-from-JK, Combinations, a Boolean Evaluation, and a Shift-Register/JK Synthesis
  4. Question 4 Excess-3 Code, a 3-Bit NAND-Only Converter, and a PAL16L8 Implementation
  5. Question 5 Even-Parity Generator for a Synchronized 5-Bit Serial Stream

Start with Question 1 →

04-BS-8 Digital Logic Circuits — December 2019
National Exams, 3 hours, closed book (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.

Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, K-maps, PAL/PLA architectures, flip-flop conversion, sequential-circuit design, code conversion; Floyd, Digital Fundamentals (11th ed., Pearson) — logic gates, shift registers, flip-flop characteristic tables, parity generation.