Question 1 of 5: Synchronous Up-Down Counter (Non-Binary Sequences)
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
04-BS-8 Digital Logic Circuits — December 2019
National Exams, 3 hours, closed book (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.
The up cycle {0,2,4,5,6} and down cycle {7,5,4,3,1} together use every one of the 8 three-bit codes exactly once, sharing only states 4 and 5. The question defines a next state for each state in its own cycle's direction only (e.g. state 0 has no down-direction (C=1) neighbour, since 0 is not in the down cycle). These "wrong-direction" transitions (from 0,2,6 when C=1; from 1,3,7 when C=0) are treated as don't-cares in the K-map — the standard, and only self-consistent, reading for a counter whose two prescribed cycles do not cover all 16 (state,C) combinations between them.
Given. Up cycle (C=0): $0\to2\to4\to5\to6\to0$. Down cycle (C=1): $7\to5\to4\to3\to1\to7$. Negative edge-triggered D flip-flops, state = $Q_2Q_1Q_0$ (natural binary code equal to the decimal state shown).
Find. (a) State diagram. (b) D flip-flop state equations $D_2,D_1,D_0$, minimized. (c) Circuit implementation.
Approach. Draw both cycles on one 8-state diagram (they share states 4 and 5); build the 16-row $(Q_2,Q_1,Q_0,C)\to(D_2,D_1,D_0)$ transition table directly from the two given cycles, marking every "wrong-direction" row as a don't-care; Quine–McCluskey-minimize each $D_i$ with those don't-cares, brute-force-verify the result against every defined row, then implement with 3 negative-edge D flip-flops driven by the minimized combinational logic.
Part (a) — state diagram. The two cycles are drawn together below: the blue arrows are the up cycle (active when $C=0$), the red arrows are the down cycle (active when $C=1$); states 4 and 5 are the only states common to both cycles, so they are the only states where the counter can change direction without first completing a full lap of its current cycle.
Fig. Q1(a) — combined state diagram for the up-down counter. Blue = up cycle (C=0): 0-2-4-5-6-0. Red = down cycle (C=1): 7-5-4-3-1-7.
Part (b) — state equations. Building the 16-row transition table from the diagram above (8 states × 2 directions, 8 rows defined per direction, 8 don't-care rows for the wrong-direction cases) and Quine–McCluskey-minimizing each output bit with those don't-cares gives $$D_2 = Q_2Q_1'C' + Q_2Q_0 + Q_2'Q_1Q_0' + Q_1'Q_0$$ $$D_1 = Q_2'Q_1' + Q_0C' + Q_0'C$$ $$\boxed{D_0 = Q_2'Q_0 + Q_1C + Q_2Q_1'Q_0'}$$ Because negative edge-triggered D flip-flops simply latch their D input on the falling clock edge, these three expressions are directly the next-state equations $Q_i^+ = D_i$.
Part (c) — circuit implementation. Three negative edge-triggered D flip-flops hold $Q_2Q_1Q_0$; a combinational "next-state logic" block realizes $D_2,D_1,D_0$ from the equations above (inputs $Q_2,Q_1,Q_0,C$) and feeds the three D inputs every clock, exactly the K-map-derived-logic→D-FF-bank→feedback template used throughout this paper.
Fig. Q1(c) — 3 negative-edge D flip-flops with feedback through the combinational next-state logic block (equations from Part (b)).
