Question 3 of 5: D-from-JK, Combinations, a Boolean Evaluation, and a Shift-Register/JK Synthesis

Question 3: D-from-JK, Combinations, a Boolean Evaluation, and a Shift-Register/JK Synthesis (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) A JK flip-flop and unrestricted gates. (b) A 5-input digital system. (c) $A=0,B=1,C=1$ in $X=(A\oplus B)'.C$. (d) Figure Q3: an 8-bit shift register whose serial output feeds (i) a 2-input XOR gate whose other input is the fed-back output of a J-K flip-flop, looping back to the shift register's own serial input, and (ii) a 2-input OR gate (the J-K's other input is the same J-K's own $Q$, fed back) driving $J$, with $K$ tied to the inverse of that same OR-gate output; the J-K is cleared to 0 initially.

Find. (a) A D flip-flop built from a JK flip-flop, minimum gates. (b) The input-combination count. (c) $X$. (d) The circuit's function, and the shift register's content after 8 clocks starting from $(11001110)_2$.

Approach. (a) Compare the JK and D characteristic tables directly. (b) $2^n$ for $n$ independent binary inputs. (c) Substitute directly. (d) Trace every wire in Figure Q3 to its physical origin, write the Boolean equations for $J$ and $K$, recognize the resulting flip-flop behaviour, then simulate the whole circuit cycle-by-cycle for the given 8-bit load.

1. Part (a) — D flip-flop from a JK flip-flop. The JK characteristic equation is $Q^+=J\bar Q+\overline{K}Q$; the D characteristic equation is simply $Q^+=D$. Setting $J=D$ and $K=D'$ (built with a single inverter) gives $Q^+=D\bar Q+\overline{D'}Q=D\bar Q+DQ=D(\bar Q+Q)=D$ — an exact match. Minimum gate count: 1 inverter (no D-from-JK conversion needs zero gates, unlike the well-known zero-gate T-from-JK conversion, because $K$ must be built as the complement of $J$).
   Fig. Q3(a) — D flip-flop from a JK flip-flop: $J=D$ direct, $K=D'$ via one inverter.
2. Part (b) — input combinations. Each of the 5 inputs is independently 0 or 1, so the number of distinct input combinations is $$2^5=\boxed{32}$$
3. Part (c) — evaluate $X$. $A\oplus B = 0\oplus 1 = 1$, so $(A\oplus B)'=0$. Then $$X = 0\cdot C = 0\cdot 1 = \boxed{0}$$
4. Part (d), Step 1 — trace the circuit and write its equations. The J-K's own $Q$ output feeds back to three places: the bottom input of the large XOR gate, the bottom input of the small OR gate, and (through the bubble drawn at the $K$ pin) directly to $K$ — i.e. $K$ is wired to the same node as $J$, through an inversion. Calling the shift register's current serial output bit "SerialOut": $$J = \text{SerialOut} + Q, \qquad K = J'$$ Since $K=J'$ always, the JK characteristic equation collapses: $Q^+=JQ'+K'Q=JQ'+JQ=J(Q'+Q)=J$ — this J-K is wired as a plain D flip-flop with $D=\text{SerialOut}+Q$, and the new bit shifted into the register every clock is $$\text{new bit in} = \text{SerialOut}\oplus Q$$

   [Figure not reproduced: Fig. Q3(d) — the circuit redrawn from the source figure, with the traced equations $J=\text{SerialOut}+Q$, $K=J'$ labelled. See the official exam paper.]

5. Part (d), Step 2 — identify the main function. While $Q=0$ (its cleared/initial value), $D=\text{SerialOut}+0=\text{SerialOut}$, so the fed-back bit passes through unchanged, and $Q$ stays 0 for as long as every bit shifted out is 0. The instant a 1 is shifted out, $Q$ becomes 1 ($Q^+=\text{SerialOut}+Q=1$) and, because $Q$ only ever appears OR'd into its own next value, it then latches at 1 permanently (until an external clear). From that point on, every subsequent bit is fed back as $\text{SerialOut}\oplus 1=\overline{\text{SerialOut}}$ — i.e. complemented. Reading the bits out of the register LSB-first (the output-side stage holds the number's least-significant bit), this is exactly the textbook shortcut for forming a 2's complement: copy bits unchanged from the LSB up through and including the first 1, then complement every bit after that. This circuit is a serial 2's-complement generator.
6. Part (d), Step 3 — worked example. Loading $(11001110)_2=206_{10}$ (output-side stage = the rightmost printed bit, 0, i.e. the number's LSB) and clearing $Q=0$, then clocking 8 times with $Q^+=\text{SerialOut}+Q$ and each new bit $=\text{SerialOut}\oplus Q$: the first bit out (0, the LSB) passes unchanged since $Q$ is still 0; the second bit out (1) is the first 1 encountered — it too passes unchanged, and $Q$ latches to 1 immediately after; every bit from the third onward is complemented. After 8 clocks the register holds $$\boxed{00110010_2 = 50_{10}}$$ which is exactly $256-206=50$, the 8-bit 2's complement of the loaded value — confirming the Step 2 identification. Final $Q=1$ (a 1 was found in the number, as it must be for any nonzero input).

   Cycle-by-cycle trace (register shown after each shift; SerialOut is the bit leaving that cycle)

   Clock	SerialOut	Q (before)	new bit in	Register after shift	Q (after)
   0 (load)	—	0	—	11001110	0
   1	0	0	0	01100111	0
   2	1	0	1	10110011	1
   3	1	1	0	01011001	1
   4	1	1	0	00101100	1
   5	0	1	1	10010110	1
   6	0	1	1	11001011	1
   7	1	1	0	01100101	1
   8	1	1	0	00110010	1