Question 4 of 5: Excess-3 Code, a 3-Bit NAND-Only Converter, and a PAL16L8 Implementation
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
04-BS-8 Digital Logic Circuits — December 2019
National Exams, 3 hours, closed book (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.
The printed exam text asks for a 3-bit input and a 3-bit output, not the standard 4-bit decimal Excess-3 code defined in part (a). A 3-bit code only spans values 0–7, so this part is answered literally as written: a 3-bit binary input $B_2B_1B_0$ (value $v=0..7$) mapped to a 3-bit output $E_2E_1E_0=(v+3)\bmod 8$ (the "add 3" rule of Excess-3, truncated to 3 bits with the carry out of the top bit simply dropped/wrapped). This is a self-contained, fully-specified 8-row combinational design exercise distinct from the true 4-bit BCD digit code defined in part (a).
Given. (a) The definition to state. (b),(c) a 3-bit input $B_2B_1B_0$ (value 0–7) to be converted to $E_2E_1E_0=(B+3)\bmod 8$.
Find. (a) A definition and one advantage. (b) The minimum-NAND-gate design. (c) A PAL16L8 implementation.
Approach. (a) State the add-3 rule and its self-complementing property. (b) Tabulate all 8 rows, K-map/QM-minimize each output bit, then convert the minimal SOP to a 2-input-NAND network sharing inverters across outputs. (c) Map each minimized product term directly onto one AND-array row of the PAL16L8, OR-summed per output by the device's fixed OR array.
Part (a) — definition and advantage. The (true, 4-bit) Excess-3 code represents each decimal digit $d\in\{0,\dots,9\}$ by the 4-bit binary value of $(d+3)$ — e.g. digit 0 → 0011, digit 9 → 1100 — hence "10-excess-3": every valid code word is the digit's natural BCD value shifted up (in excess) by 3. Advantage: Excess-3 is self-complementing — the 9's complement of a decimal digit ($9-d$) is obtained by simply inverting every bit of its Excess-3 code, with no arithmetic needed — which made it attractive for decimal subtraction by complement-addition in early BCD arithmetic units. (A second advantage: Excess-3 never uses the all-0s or all-1s code for a valid digit, which historically helped distinguish a blank/unprogrammed memory cell from a legitimate stored digit.)
Part (b), Step 1 — truth table and minimal SOP. Tabulating $E=(v+3)\bmod8$ for all 8 values of $B_2B_1B_0$ and Quine–McCluskey-minimizing each output bit:
Part (b), Step 2 — minimum 2-input-NAND-gate network. Building 3 shared inverters ($B_2',B_1',B_0'$ — $B_0'$ doubles directly as $E_0$, needing no further gate), then $E_1$ as a 2-term NAND-NAND network (3 gates: $\overline{B_1'B_0'}$, $\overline{B_1B_0}$, final NAND), and $E_2$ as a 3-term NAND-NAND network with one 3-literal term needing an extra double-negation stage (6 gates total, sharing the $B_2'$ inverter across its last two terms): 12 two-input NAND gates in total (3 shared inverters + 3 for $E_1$ + 6 for $E_2$; $E_0$ is free, it IS the $B_0'$ inverter).
Fig. Q4(b) — 2-input-NAND-only network for $E_2,E_1,E_0$ (12 gates total, inverters shared across outputs).
Part (c) — PAL16L8 implementation. Only 3 of the PAL16L8's dedicated inputs ($B_2,B_1,B_0$, each with its true and complemented column in the AND array) and 3 of its 8 outputs ($E_2,E_1,E_0$) are used; each minimized product term above becomes one AND-array row with its literals' fuses left intact (crossed in the diagram) and every other fuse in that row blown, and the fixed OR array sums the rows assigned to the same output — $E_0$ needs 1 row, $E_1$ needs 2 rows (OR'd), $E_2$ needs 3 rows (OR'd), for 6 product-term rows total out of the device's budget of up to 7 rows per output.
Fig. Q4(c) — PAL16L8 AND-array rows actually used (fuse crossings shown) for $E_2,E_1,E_0$; unused input columns, unused rows, and unused outputs are not drawn.
