Question 5 of 5: Even-Parity Generator for a Synchronized 5-Bit Serial Stream
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
04-BS-8 Digital Logic Circuits — December 2019
National Exams, 3 hours, closed book (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.
The design below is deliberately decomposed into two small, independent synchronous elements rather than one monolithic multi-variable state machine: a 6-state bit-position counter (IDLE, POS1…POS5) that knows only "which of the 5 bits is currently on the input," reset to POS1 by the Synch pulse, and a single parity accumulator D flip-flop that knows only "the running XOR of the bits seen so far." This is the standard textbook decomposition for a counter-gated datapath (it keeps the state diagram in part (a) to a manageable 6 states instead of an equivalent but needlessly large ~11-state combined machine), and it is verified to compute exactly $\text{even}=d_1\oplus d_2\oplus d_3\oplus d_4\oplus d_5$ — the correct even-parity bit — over many randomized 5-bit frames.
Given. A 5-bit serial data stream, LSB first, preceded by a one-clock-cycle Synch pulse; data bits are stable across each positive clock edge (they change on the negative edges).
Find. (a) State diagram/table. (b) D flip-flop design. (c) Circuit diagram.
Approach. Track bit-position with a small counter (loaded to POS1 by Synch, advancing every clock, returning to IDLE after POS5) and accumulate parity with one D flip-flop cleared synchronously at the start of every frame; output even combinationally (Mealy) as the running parity XOR'd with the current bit, gated on only while in POS5 — this delivers the required result during the 5th bit's own cycle, with no extra clock of latency.
Part (a) — state diagram and table. Six states: IDLE (waiting for Synch), POS1…POS5 (currently on bit 1…5 of the frame). From IDLE, $S=0$ self-loops; $S=1$ advances to POS1. POS1 through POS4 unconditionally advance to the next position each clock; POS5 unconditionally returns to IDLE. The parity value itself is tracked separately (Part (b)) rather than folded into this diagram, keeping the state count at 6 instead of an equivalent ~11-state machine that also encodes the running parity in each state.
State table (C2C1C0 encoding: IDLE=000, POS1=001,…,POS5=101)
Present state
S
Next state
IDLE (000)
0
IDLE (000)
IDLE (000)
1
POS1 (001)
POS1 (001)
×
POS2 (010)
POS2 (010)
×
POS3 (011)
POS3 (011)
×
POS4 (100)
POS4 (100)
×
POS5 (101)
POS5 (101)
×
IDLE (000)
Part (b), Step 1 — counter D-equations. Encoding the states as shown and Quine–McCluskey-minimizing each bit over the 16-row $(C_2,C_1,C_0,S)$ table (codes 110,111 unused, don't-cares): $$C_2^+ = C_1C_0 + C_2C_0' \qquad C_1^+ = C_2'C_1'C_0 + C_1C_0' \qquad \boxed{C_0^+ = C_1C_0' + C_0'S + C_2C_0'}$$
Part (b), Step 2 — parity accumulator. One D flip-flop $P$ holds the running parity. Its synchronous clear input is driven by $\text{CLR}=C_2'C_1'C_0'{\cdot}S$ (true only on the IDLE$\to$POS1 transition cycle, i.e. exactly when a new frame is starting), so $P$ is guaranteed 0 on entry to POS1; every other cycle it simply accumulates, $$D_P = \text{data}\oplus P$$ Because the flip-flop's own CLR pin handles the frame-boundary reset, no extra gating of $D_P$ is needed.
Part (b)/(c), Step 3 — the "even" output, combinational (Mealy). Waiting for $P$ to update would deliver the completed parity one cycle after bit 5, but the question requires it during bit 5's own cycle. The fix is a combinational (Mealy) output: since $P$ already holds the XOR of bits 1–4 by the time POS5 is reached, $$\text{even} = (\text{POS5 decode}){\cdot}(P\oplus\text{data}) = C_2C_1'C_0'{\cdot}(P\oplus\text{data})$$ computed and output the instant bit 5 is on the input, with no extra clock of delay — this equals $d_1\oplus d_2\oplus d_3\oplus d_4\oplus d_5$, the correct even-parity bit.
Fig. Q5(c) — 3 D flip-flops for the bit-position counter, 1 D flip-flop (with synchronous CLR) for the parity accumulator, and the combinational "even" output gate.
