Traffic Light Controller: 04-BS-8, Undated paper, Q2

Question 2: Traffic Light Controller (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. 1 Hz clock; repeating 30-second cycle: GREEN alone 14 s, GREEN&YELLOW together 4 s, RED alone 12 s ($14+4+12=30$); three active-low LED outputs.

Find. A state-machine-plus-decoder design (counter + combinational decode, as the question's hint suggests) that produces the three active-low drive signals with the correct timing, repeating indefinitely.

The state machine is a mod-30 binary counter (its own count IS the state); the decoder maps count ranges directly onto the three LED-drive signals.

Approach. Use a 5-bit binary counter (5 bits since $2^4=16<30\le32=2^5$) as the "state machine," synchronously reset to 0 when it reaches 29, and derive the three active-high internal enables GREEN, YELLOW, RED as minimized Boolean functions of the counter bits $C_4C_3C_2C_1C_0$ (values 30, 31 unused → don't-cares); the LED outputs are simply these enables' complements.

Counter sizing and reset. $C_4$ is the 16's bit; counting 0–29 needs 5 bits with a synchronous "load 0" fired when the count equals 29 (detected combinationally as $C_4C_3C_2C_1C_0=11101$), so the very next clock returns to 00000 instead of continuing to 30.
RED region (count 18–29). Values 16–31 all have $C_4{=}1$; excluding 16,17 (whose lower nibble is 0000/0001) leaves exactly 18–29 (plus don't-cares 30,31): $$\text{RED} = C_4\,(C_3+C_2+C_1)$$
GREEN region (count 0–17, i.e. green-only PLUS green+yellow). By De Morgan, GREEN is simply "not RED": $$\text{GREEN} = \overline{C_4\,(C_3+C_2+C_1)} = C_4' + C_3'C_2'C_1'$$
YELLOW region (count 14–17 only). This is the 2-count tail of the $C_4{=}0$ block (14,15) plus the 2-count head of the $C_4{=}1$ block (16,17), so it splits into two product terms with $C_0$ free in both: $$\text{YELLOW} = C_4' C_3 C_2 C_1 + C_4 C_3' C_2' C_1'$$
Drive the LEDs. Active-low outputs are the complements of the enables just derived: $\text{GREEN\_L}=\text{GREEN}'$, $\text{YELLOW\_L}=\text{YELLOW}'$, $\text{RED\_L}=\text{RED}'$ — each a single inverter (or fold the inversion into the last gate of each decoder tree).

Check

All three enables and the reset comparator were exhaustively checked against every one of the 30 reachable counts (0–29): GREEN stays high for exactly 14 counts, YELLOW for exactly 4, RED for exactly 12, with no two enables ever high—wait, GREEN and YELLOW ARE both high together for counts 14–17 by design (that is the "both LEDs on" phase); RED never overlaps either.

Final results — Question 2
Item	Result
Counter	5-bit synchronous, mod-30 (reset at count=29→0)
GREEN enable	$C_4' + C_3'C_2'C_1'$ — counts 0–17 (18 s)
YELLOW enable	$C_4'C_3C_2C_1 + C_4C_3'C_2'C_1'$ — counts 14–17 (4 s)
RED enable	$C_4(C_3+C_2+C_1)$ — counts 18–29 (12 s)
Cycle length	30 s (14+4+12), repeats indefinitely

Concept & Theory

Topic: Timer-driven traffic-light sequencing via a modulo-N counter and a combinational decoder (the classic "counter as the state register" pattern).

Key relations: A free-running counter's own count IS a Moore state; any interval decode reduces to range comparison, and consecutive ranges sharing a high bit ($C_4$) collapse into few product terms exactly like a K-map with a large "don't care" tail (30, 31 unused).

Why this works: Splitting 30 counts into 18 (green-eligible) and 12 (red) lines up perfectly on the $C_4$ boundary (16), so GREEN needs no more logic than "NOT red"; YELLOW is the narrow band straddling that same boundary, which is why it naturally splits into two product terms instead of one contiguous range.

Common pitfall: Forgetting the synchronous reset at count 29 and letting a naive 5-bit counter free-run to 31 before wrapping — that silently stretches the cycle from 30 s to 32 s and creates two invalid states (30, 31) with undefined LED behaviour unless they are captured as don't-cares (as done here).

Source: Mano & Ciletti, Digital Design §5 (registers and counters, decoders); Floyd, Digital Fundamentals § on decoders/comparators.

Question 2 of 5: Traffic Light Controller

Question 2: Traffic Light Controller (25 marks)