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04-BS-8 · Undated paper

Question 4 of 5: Boolean Simplification and K-map Minimization

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

04-BS-8 Digital Logic Circuits — May 2019
National Exams, closed book (approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks; all five are solved below for completeness.

Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, K-maps, PAL/PLA architectures, flip-flop conversion, sequential-circuit design, code conversion; Floyd, Digital Fundamentals (11th ed., Pearson) — logic gates, shift registers, flip-flop characteristic tables, parity generation.

Question 4: Boolean Simplification and K-map Minimization (24 marks, sub-mark split uncertain — see Verify note)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Part (a): a 2-input circuit — input $A$ feeds one AND input directly, input $B$ feeds the other AND input through an inverter; the AND output feeds a final inverter producing $X$. Part (b): $Y(A,B,C,D)=\sum M(1,2,4,5,6,7,10,11,15)$ (9 minterms out of 16, remaining 7 are 0-terms — no don't-cares).

Find. Part (a) the simplified expression for $X$. Part (b)(i) the K-map. (ii) minimal POS for $Y$. (iii) a NOR-gate-only realization of that POS.

  1. Part (a). Reading the gates directly: $X = \overline{A\cdot \bar B}$. Applying De Morgan's theorem, $$X = \overline{A\cdot\bar B} = \bar A + B$$ — a single 2-input OR gate (with $A$ inverted) replaces the original AND-then-NOT pair.
  2. Part (b)(i) — K-map. Plot all 16 minterms on a 4-variable map (rows $AB$, columns $CD$, both in Gray-code order) and mark the 9 given minterms as 1, the remaining 7 (0,3,8,9,12,13,14) as 0.
AB \ CD 00 01 11 10 00 01 11 10 0m0 1m1 0m3 1m2 1m4 1m5 1m7 1m6 0m12 0m13 1m15 0m14 0m8 0m9 1m11 1m10 B'C'D' → sum-term (B+C+D) A'B'CD → sum-term (A+B+C'+D') ABD' → sum-term (A'+B'+D) AC' → sum-term (A'+C)
Part (b)(i). The four highlighted groups cover every 0-cell of Y (equivalently, every 1-cell of the complement $\bar Y$); grouping ZEROS is the standard shortcut to a POS result.
  1. Part (b)(ii) — POS via the complement. Minimizing the 0-cells (i.e. $\bar Y$) directly is exactly as valid as minimizing the 1-cells, and each resulting product term of $\bar Y$ becomes one OR-sum-term of $Y$ under De Morgan. The four essential groups above (each covers at least one 0-cell no other group reaches, so all four are required) give $$\bar Y = B'C'D' + A'B'CD + ABD' + AC'$$ Complementing term-by-term: $$\boxed{Y = (B+C+D)(A+B+C'+D')(A'+B'+D)(A'+C)}$$
  2. Part (b)(iii) — NOR-only realization. A NOR-NOR two-level network realizes a POS expression exactly as a NAND-NAND network realizes an SOP: feed each sum-term's literals into its own first-level NOR gate (a NOR gate outputs the complement of the OR of its inputs, i.e. the complement of that one sum-term); then a single second-level NOR gate combines the four first-level outputs, since $\text{NOR}(s_1',s_2',s_3',s_4') = (s_1'+s_2'+s_3'+s_4')' = s_1 s_2 s_3 s_4 = Y$. The complemented literals $A',B',C',D'$ needed inside some sum-terms are each generated by a 2-input NOR gate with its two inputs tied together (NOR(x,x)$=\bar x$), so the whole network uses NOR gates exclusively.
NOR-only realisation of Y = (B+C+D)(A+B+C'+D')(A'+B'+D)(A'+C) Inverters (2-input NOR, inputs tied) supply A', B', C', D': A A' B B' C C' D D' (B+C+D)' B C D (A+B+C'+D')' A B C' D' (A'+B'+D)' A' B' D (A'+C)' A' C Y Each first-level NOR outputs the complement of one POS sum-term; the final NOR ORs-then-inverts those four complements back into their product — i.e. Y.
Part (b)(iii). Four inverters (NOR-tied) plus four first-level NOR gates plus one combining NOR gate — nine NOR gates total, none of any other type.
Check

The printed sub-marks (5+4+8+7=24) fall one short of this question's stated 25; this does not affect the technical answer.

Final results — Question 4
ItemResult
(a) X$\bar A + B$
(b)(ii) Y, POS$(B+C+D)(A+B+C'+D')(A'+B'+D)(A'+C)$
(b)(iii) gate count9 NOR gates (4 inverters + 4 first-level + 1 final)