JK Flip-Flop Synthesis and 2's-Complement Circuit: 04-BS-8, Undated paper, Q5

Question 5: JK Flip-Flop Synthesis and 2's-Complement Circuit (20 marks printed — see Verify note)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

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The printed question is internally ambiguous in two places: Figure Q5 is described with inputs J, K, Clock while the question text asks for behaviour "for all combinations of inputs A and B" (two waveform traces, not J/K) — the most defensible reading, taken here, is that A and B ARE the flip-flop's J and K inputs under this question's own labelling (a common textbook variant). Sub-part (b)'s "12 binary numbers" is very likely a misprint of "n-bit binary numbers" (a numeral where a variable belongs) and is treated as such below, worked for a representative 4-bit word. Printed sub-marks (10+10=20) are 5 short of this question's nominal 25; both gaps are flagged rather than silently patched.

Given. Part (a): two 3-input AND gates — one gated by ($A\equiv J$, CLK, $\bar Q$ feedback), the other by ($B\equiv K$, CLK, $Q$ feedback) — feeding a cross-coupled 2-input NOR latch that outputs $Q,\bar Q$; clock triangle drawn for a rising-edge transition. Part (b): an $n$-bit unsigned binary number $b_{n-1}\ldots b_1b_0$ (worked below for $n=4$).

Find. (a) the characteristic (next-state) table for all four (A,B) combinations and the active clock edge. (b) a combinational (no adder) circuit producing the 2's complement.

Part (a). The AND gates are enabled only while CLK is asserted; whichever one is enabled steers the cross-coupled NOR latch, giving the classic gated-latch synthesis of a JK flip-flop.

Part (a) — synthesis. With CLK asserted: if $A{=}1,B{=}0$ the top AND gate (gated by $\bar Q$) can fire, forcing the latch to $Q{=}1$ (set); if $A{=}0,B{=}1$ the bottom AND gate (gated by $Q$) can fire, forcing $Q{=}0$ (reset); if $A{=}B{=}0$ neither AND gate fires and the latch holds its last value; if $A{=}B{=}1$ both AND gates are enabled but each is gated by the OTHER'S present output ($\bar Q$ and $Q$ respectively), so exactly one fires depending on the current state, flipping it — a toggle. This reproduces the JK characteristic table exactly.
Active clock transition. The circuit is level-sensitive while CLK is asserted; drawn with a rising-edge clock triangle at Figure Q5, the design is read as triggering on the rising edge of CLK, i.e. the state changes are latched in at that instant and held stable while CLK stays high (avoiding the 1s-catching race by treating CLK as a narrow pulse synchronized to the rising edge, the standard simplification used when this gate topology is taught as "the" edge-triggered JK).

All four (A,B) combinations reproduce the standard JK table: hold, reset, set, toggle.

Part (b) — combinational 2's complement. The bit-manipulation shortcut (no adder needed): scanning from the LSB upward, copy every bit unchanged up to and including the first 1 encountered; invert every bit above it. Formalize with a running OR $P_i=b_0+b_1+\cdots+b_{i-1}$ (has a 1 already occurred strictly below bit $i$?), $P_0=0$: $$y_i = b_i \oplus P_i,\qquad P_i = P_{i-1}+b_{i-1}$$ Each $P_i$ costs one more OR gate feeding forward (a ripple chain), and each output bit is one XOR gate.

Part (b). Worked for $n=4$; the same $P_i=P_{i-1}+b_{i-1}$, $y_i=b_i\oplus P_i$ pattern extends to any word width $n$ by adding one more OR/XOR stage per bit.

Worked example: $B=0110_2=6_{10}$. $P_0{=}0\Rightarrow y_0{=}0{\oplus}0{=}0$. $P_1{=}P_0{+}b_0{=}0\Rightarrow y_1{=}1{\oplus}0{=}1$. $P_2{=}P_1{+}b_1{=}0{+}1{=}1\Rightarrow y_2{=}1{\oplus}1{=}0$. $P_3{=}P_2{+}b_2{=}1{+}1{=}1\Rightarrow y_3{=}0{\oplus}1{=}1$. Result $1010_2$ — the correctly-signed 2's complement of $+6$ is $-6$ (4-bit signed value $1010_2=-6$), confirming the circuit.

Final results — Question 5
Item	Result
(a) Q(next), A=B=0	Q (hold)
(a) Q(next), A=0,B=1	0 (reset)
(a) Q(next), A=1,B=0	1 (set)
(a) Q(next), A=B=1	Q̄ (toggle)
(a) Active edge	Rising edge of CLK
(b) 2's-complement rule	$y_i=b_i\oplus P_i,\ P_i=P_{i-1}+b_{i-1},\ P_0=0$
(b) Example	$0110_2\to1010_2$ ($+6\to-6$)

Concept & Theory

Topic: Gate-level JK flip-flop synthesis from an AND-gated NOR latch, and the bit-manipulation (adder-free) 2's-complement circuit.

Key relations: JK characteristic equation $Q^+ = J\bar Q + \bar K Q$; 2's complement $= $ (invert all bits) $+1$, which is equivalent bit-for-bit to "copy through the first 1, invert above it" — the running-OR/XOR identity proved here.

Why this works: The JK's toggle case is exactly what makes it strictly more general than an SR latch: feeding each AND gate its OWN complementary state bit ($\bar Q$ for the set path, $Q$ for the reset path) breaks the SR latch's forbidden $S{=}R{=}1$ state into a well-defined toggle instead. The 2's-complement shortcut works because adding 1 to the inverted bits only ever produces a carry-ripple that stops at the first inverted-0-that-was-a-1, i.e. exactly the bits below the original first 1 — which the direct copy-then-invert rule already leaves untouched.

Common pitfall: For (a), confusing a level-sensitive gated latch with a true edge-triggered flip-flop (the simple AND-NOR topology shown is susceptible to multiple triggering if CLK stays high while J/K change; a real product uses a master-slave or edge-detector pair) — a source of "why doesn't this behave like a 7476" confusion. For (b), forgetting that bit 0 is ALWAYS copied unchanged ($P_0=0$ unconditionally), which some students mistakenly invert.

Source: Mano & Ciletti, Digital Design §5 (flip-flop synthesis, arithmetic circuits, 2's-complement); Floyd, Digital Fundamentals § on flip-flop characteristic tables and adders/subtractors.

Question 5 of 5: JK Flip-Flop Synthesis and 2's-Complement Circuit

Question 5: JK Flip-Flop Synthesis and 2's-Complement Circuit (20 marks printed — see Verify note)