Synchronous Even-Number Counter: 04-BS-8, Undated paper, Q3

Question 3: Synchronous Even-Number Counter (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Displayed sequence 0,2,4,6,8,10,12,14, then repeat — 8 distinct even values, each one greater than the last by 2. Negative-edge-triggered flip-flops, "of your choice."

Find. Part (a) a state table for the 8-state cycle. Part (b) minimized next-state (excitation) equations. Part (c) the wired counter circuit.

Approach. Since every displayed value is even, its binary representation always has bit 0 equal to 0 — so the counter only needs to generate the internal value $N=\text{count}/2 = 0,1,\dots,7$ in ordinary 3-bit binary and report $2N$ (i.e. hard-wire a 0 as the least-significant display digit). That collapses the problem to a standard mod-8 binary up-counter, letting JK flip-flops be used in their simplest toggle mode.

Part (a) — state table. Let $Q_2Q_1Q_0$ be the internal 3-bit state (displayed value $=2\times Q_2Q_1Q_0$). The required state sequence is the ordinary binary count: $000\to001\to010\to011\to100\to101\to110\to111\to000\ (\text{repeat})$ — i.e. every state's next state is (present value $+1)\bmod 8$.
Part (b) — JK excitation. Choosing JK flip-flops, the JK excitation table ($Q\to Q^+$: $0\to0\Rightarrow J{=}0,K{=}d$; $0\to1\Rightarrow J{=}1,K{=}d$; $1\to0\Rightarrow J{=}d,K{=}1$; $1\to1\Rightarrow J{=}d,K{=}0$) applied to a plain binary up-count gives the textbook toggle pattern directly, with every don't-care resolved to reproduce a pure toggle-on-carry: $$J_0=K_0=1,\qquad J_1=K_1=Q_0,\qquad J_2=K_2=Q_1Q_0$$ Bit 0 always toggles; bit 1 toggles only when $Q_0{=}1$ (i.e. on a carry out of bit 0); bit 2 toggles only when both lower bits are 1 (carry out of bit 1) — exactly ripple-carry logic implemented synchronously.
Part (c) — circuit. Tie $J_0=K_0=1$; feed $Q_0$ into $J_1=K_1$; AND $Q_1\cdot Q_0$ into $J_2=K_2$; drive all three flip-flops from the same negative-edge clock so every bit updates simultaneously (synchronous, not ripple).

Part (c). All three JK flip-flops share one negative-edge clock; only the toggle-enable ANDing distinguishes bit 2 from a plain ripple pattern, keeping the design fully synchronous.

Final results — Question 3
Item	Result
Internal state	3-bit binary up-counter $Q_2Q_1Q_0=000\ldots111$
J0, K0	1, 1 (always toggle)
J1, K1	$Q_0$, $Q_0$
J2, K2	$Q_1Q_0$, $Q_1Q_0$
Displayed sequence	$2\times(Q_2Q_1Q_0)_{10} = 0,2,4,6,8,10,12,14$, repeat

Concept & Theory

Topic: Synchronous binary counter design via the JK excitation table, exploiting a fixed low-order bit to realize a "count by 2" display.

Key relations: JK excitation table ($0\to0$: $Jd,K_d$ generalize to $J{=}0,K{=}d$; etc.); synchronous ripple-carry toggle pattern $J_i=K_i=Q_{i-1}Q_{i-2}\cdots Q_0$ for a binary up-counter.

Why this works: Because the displayed sequence is exactly "count by 2," the least-significant displayed bit is always 0 and carries no information — the entire design reduces to a completely ordinary mod-8 binary counter on the remaining 3 bits, with the display simply shifting that count left by one bit position.

Common pitfall: Trying to design 4 flip-flops for the literal 4-bit displayed values (0000, 0010, 0100, …) and re-deriving next-state logic for a bit that is provably always 0 — wasted work that also risks an inconsistent equation if the always-0 bit is treated as a free variable.

Source: Mano & Ciletti, Digital Design §5 (excitation tables, counter design); Floyd, Digital Fundamentals § on synchronous counters.

Question 3 of 5: Synchronous Even-Number Counter

Question 3: Synchronous Even-Number Counter (25 marks)