Question 2 of 7: MOS Cascade — Diode-Loaded CS Stage Buffered by a Source Follower
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Comp-A1, Electronics — National Exams, December 2019. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource). Where a diode is used without a stated drop, $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters, MOSFET/BJT small-signal amplifiers, active loads, op-amp imperfections and oscillators, CMOS logic, DACs) — the single reference text covering every question on this paper.
Question 2: MOS Cascade — Diode-Loaded CS Stage Buffered by a Source Follower (20 marks)
Given. $Q_1$ (NMOS, gate$=V_i$, source grounded, drain$=$node $V$) is loaded by $Q_2$ (PMOS, source$=5\text{V}$, diode-connected: gate$=$drain$=$node $V$). Node $V$ drives the gate of $Q_3$ (NMOS source follower: drain$=5\text{V}$, source$=V_o$, with resistor $R$ from $V_o$ to ground).
Given data
Quantity
Value
$k_n'(W/L)_1=k_n'(W/L)_3$
$1\text{ mA/V}^2$
$k_p'(W/L)_2$
$1/3\text{ mA/V}^2$
$V_{tn}=|V_{tp}|$
1.0V
$V_A$ (each device, AC only)
80V
$V_{DD}$
5V
$I_{D,Q3}$ (target)
0.5mA
Find. $R$ for $I_{D,Q3}=0.5\text{mA}$; small-signal model; $R_i$, $R_o$; overall AC voltage gain $v_o/v_i$.
Check — engineering assumption
The printed figure gives $Q_1$'s gate node "$V_i$" with no stated DC value. The design is fully determined only if the first-stage bias current equals the stated $I_{D,Q3}=0.5\text{mA}$ target throughout the cascade — this is confirmed self-consistently below, since it reproduces a clean $V_{OV}=1.0\text{V}$ for both NMOS stages (Q1 and Q3), which would be an unlikely coincidence if the intended bias were anything else. Solved on that basis.
Approach. KCL at node $V$ forces $I_{D1}=I_{D2}$ (Q3's gate draws no DC current); take this common current, and $I_{D,Q3}$, all equal to the stated 0.5mA design point. Compute each device's $V_{OV}$, get node $V$ from $Q_2$'s diode equation, get $V_o$ from $Q_3$'s diode-connected-like source-follower equation, then $R=V_o/I_{D,Q3}$. For the AC part, replace $Q_2$ with its diode-connected resistance and $Q_3$ with its source-follower gain formula.
Part (a) — DC bias and $R$. With $I=0.5\text{mA}$ in all three branches:
$$V_{OV,1}=\sqrt{\frac{2I}{k_n'(W/L)_1}}=\sqrt{\frac{2(0.5\text{mA})}{1\text{mA/V}^2}}=\boxed{1.000\text{ V}}\ \ (\Rightarrow V_i|_{DC}=V_{tn}+V_{OV,1}=2.0\text{V})$$
$$V_{OV,2}=\sqrt{\frac{2I}{k_p'(W/L)_2}}=\sqrt{\frac{2(0.5\text{mA})}{1/3\text{mA/V}^2}}=1.732\text{ V}\ \Rightarrow\ V_{SG2}=1+1.732=2.732\text{V}$$
$$V(\text{node})=V_{DD}-V_{SG2}=5-2.732=\boxed{2.268\text{ V}}$$
$$V_{OV,3}=\sqrt{\frac{2I}{k_n'(W/L)_3}}=1.000\text{V}\ \Rightarrow\ V_{GS3}=1+1=2.0\text{V}$$
$$V_o=V(\text{node})-V_{GS3}=2.268-2.000=0.268\text{V}\quad\Rightarrow\quad R=\frac{V_o}{I_{D,Q3}}=\frac{0.268}{0.5\text{mA}}=\boxed{536\ \Omega}$$
Part (b) — small-signal parameters. $g_m=2I_D/V_{OV}$, $r_o=V_A/I_D$:
$$g_{m1}=g_{m3}=\frac{2(0.5\text{mA})}{1.0\text{V}}=\boxed{1.000\text{ mA/V}},\qquad g_{m2}=\frac{2(0.5\text{mA})}{1.732\text{V}}=0.577\text{ mA/V}$$
$$r_{o1}=r_{o2}=r_{o3}=\frac{80\text{V}}{0.5\text{mA}}=\boxed{160\text{ k}\Omega\text{ (each)}}$$
$Q_2$, diode-connected, presents $1/g_{m2}\|r_{o2}=1.71\text{k}\Omega$ at node $V$; $Q_3$ is a source follower loaded by $R$.
Fig. Q2-b — Small-signal block view. Stage 1 is a common-source amplifier whose drain load is $Q_2$'s diode-connected small-signal resistance in parallel with its own $r_{o1}$; stage 2 is a unity-ish source follower loaded by $r_{o3}\|R$.
Part (c) — input and output resistance. $Q_1$'s gate draws no current, so $R_i=\infty$. The output resistance (looking into $v_o$, with $v_i=0$) is the parallel combination of $R$, $r_{o3}$ and the follower's own $1/g_{m3}$:
$$R_o=\left(\frac{1}{g_{m3}}\right)\Big\|r_{o3}\Big\|R=\boxed{348\ \Omega}$$
Part (d) — overall AC gain. Stage 1: $R_v=r_{o1}\|(1/g_{m2}\|r_{o2})=1.695\text{k}\Omega$, so
$$A_{v1}=-g_{m1}R_v=-(1.00\text{mA/V})(1.695\text{k}\Omega)=-1.695\text{ V/V}$$
Stage 2 (source follower with $R_L'=r_{o3}\|R=534\,\Omega$):
$$A_{v2}=\frac{g_{m3}R_L'}{1+g_{m3}R_L'}=\frac{(1.00\text{mA/V})(534\,\Omega)}{1+(1.00\text{mA/V})(534\,\Omega)}=0.348\text{ V/V}$$
$$A_v=\frac{v_o}{v_i}=A_{v1}A_{v2}=(-1.695)(0.348)=\boxed{-0.590\text{ V/V}}$$
The small load resistor $R=536\,\Omega$ (needed to hit the 0.5mA bias target) also strongly attenuates the follower stage, so despite the first stage's respectable $-1.7$ gain, the overall stage-to-stage gain is well below unity in magnitude.
