Question 6 of 7: Symmetric CMOS Inverter — Sizing, VTC and Speed

Question 6: Symmetric CMOS Inverter — Sizing, VTC and Speed (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Standard CMOS inverter: $Q_P$ source at $V_{DD}=5\text{V}$, $Q_N$ source at ground, gates tied to $V_I$, drains tied to $V_O$.

Find. $(W/L)_N,(W/L)_P$ for a symmetric VTC; the VTC shape with operating regions; the maximum external load capacitance for $t_p<200\text{ps}$; a CMOS realization of $Y=A\bar B$.

Approach. With $V_{tn}=|V_{tp}|$, a symmetric VTC (switching threshold exactly at $V_{DD}/2$, equal noise margins) requires equal NMOS/PMOS drive strength, $k_n'(W/L)_N=k_p'(W/L)_P$; size at minimum length, then use the equal-strength design to get equal (and hence average-able) switching resistances for the delay estimate.

1. Part (a) — sizing. Symmetric switching point ($V_M=V_{DD}/2$) requires matched drive: $$k_n'\Big(\frac{W}{L}\Big)_N=k_p'\Big(\frac{W}{L}\Big)_P\ \Rightarrow\ \Big(\frac{W}{L}\Big)_P=\frac{k_n'}{k_p'}\Big(\frac{W}{L}\Big)_N=\frac{50}{20}\Big(\frac{W}{L}\Big)_N=2.5\Big(\frac{W}{L}\Big)_N$$ Choosing the minimum NMOS size $(W/L)_N=1$ ($W_N=L_N=1\mu\text{m}$): $$\boxed{(W/L)_N=1\ (W_N=1\mu\text{m}),\qquad (W/L)_P=2.5\ (W_P=2.5\mu\text{m},\ L_P=1\mu\text{m})}$$
2. Part (b) — VTC regions. Sketched below: for $V_I\lt V_{tn}=1\text{V}$, $Q_N$ is cut off and $Q_P$ triode $\Rightarrow V_O=V_{DD}=5\text{V}$. For $1\text{V}\lt V_I\lt V_M=2.5\text{V}$, $Q_N$ saturation, $Q_P$ triode. Exactly at $V_M=2.5\text{V}$ both devices are in saturation (the steep transition region). For $2.5\text{V}\lt V_I\lt 4\text{V}$, $Q_N$ triode, $Q_P$ saturation. For $V_I\gt V_{DD}-|V_{tp}|=4\text{V}$, $Q_P$ cuts off, $Q_N$ triode $\Rightarrow V_O=0$.

3. Part (c) — maximum load capacitance for $t_p<200\text{ps}$. Estimate each transistor's "on" resistance while fully enhanced ($V_{GS}=V_{DD}$), using the standard linear-region approximation $R_{on}\approx1/[k'(W/L)(V_{DD}-V_t)]$: $$R_{on,N}=\frac{1}{k_n'(W/L)_N(V_{DD}-V_{tn})}=\frac1{(50\mu\text{A/V}^2)(1)(4\text{V})}=5.00\text{k}\Omega$$ $$R_{on,P}=\frac{1}{k_p'(W/L)_P(V_{DD}-|V_{tp}|)}=\frac1{(20\mu\text{A/V}^2)(2.5)(4\text{V})}=5.00\text{k}\Omega\ \ (\text{equal, by the symmetric design})$$ Using $t_p\approx0.69\,R_{on}\,C_L$ (equal $t_{pHL}=t_{pLH}$ since $R_{on,N}=R_{on,P}$): $$C_{L,\max}=\frac{t_p}{0.69\,R_{on}}=\frac{200\text{ps}}{0.69(5\text{k}\Omega)}=\boxed{58.0\text{ fF}}$$ The gate's own parasitic (input) capacitance, using the given $C_{ox}$ and the sized areas, is $$C_{self}=C_{ox}(W_NL_N+W_PL_P)=(1\text{fF}/\mu\text{m}^2)(1+2.5)\mu\text{m}^2=3.5\text{fF}$$ — small next to 58fF, so the external drivable load is $\boxed{\approx54.5\text{ fF}}$ once the inverter's own input capacitance is subtracted from the 58fF budget.
4. Part (d) — synthesizing $Y=A\bar B$. The complement of the target is $\overline{A\bar B}=\bar A+B$ (De Morgan). A single complementary CMOS gate directly realizes $\overline{A\bar B}$ at its output if the PDN implements $\bar A+B$ as an OR (parallel NMOS) and the PUN implements the dual AND (series PMOS) — but $Y$ itself (not its complement) is wanted, so build: (i) one inverter producing $\bar A$ from $A$; (ii) a complex gate with PDN $=$ NMOS($\bar A$) $\|$ NMOS($B$) to ground, and PUN $=$ PMOS($\bar A$) in series with PMOS($B$) to $V_{DD}$. Check: PUN conducts (pulls $Y$ high) only when both PMOS are on, i.e. $\bar A=0$ and $B=0$, i.e. $A=1,B=0$ — exactly $Y=A\bar B=1$. PDN conducts (pulls low) whenever $\bar A=1$ or $B=1$, i.e. whenever $A\bar B=0$. Total: 1 inverter (2 transistors) + 1 complex gate (4 transistors) = 6 transistors, all sized per the same $(W/L)_N=1$, $(W/L)_P=2.5$ ratio (each series PMOS in the complex gate sized $2\times$ up, i.e. $(W/L)_P=5$, to preserve equal worst-case drive with two devices in series).