Question 4 of 7: Split-Supply Common-Emitter Amplifier
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Comp-A1, Electronics — National Exams, December 2019. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource). Where a diode is used without a stated drop, $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters, MOSFET/BJT small-signal amplifiers, active loads, op-amp imperfections and oscillators, CMOS logic, DACs) — the single reference text covering every question on this paper.
The figure caption's explicit design current $I=1\text{mA}$ is taken as the quiescent collector/emitter current directly (the same convention every other question on this paper uses to state its bias point) rather than re-derived from the sketched $100\text{k}\Omega$ base resistor, which does not self-consistently reproduce exactly 1mA and is more likely an imprecise value for the real bias network.
Given. NPN $Q_1$: source $V_s$ with $R_s=100\,\Omega$ AC-couples into the base; base also returns to ground through a bias resistor. Collector to $+10\text{V}$ via $R_C=5\text{k}\Omega$; emitter to $-10\text{V}$ via $R_E=5\text{k}\Omega$; output taken from the collector, AC-coupled to $R_L=5\text{k}\Omega$.
Given data
Quantity
Value
$I$ (quiescent $I_C\approx I_E$)
1mA
$\beta$
100
$V_A$
100V
$V_T$
25mV
$R_C=R_E=R_L$
$5\text{k}\Omega$ each
Supplies
$\pm10\text{V}$
Find. $V_B,V_C,V_E$; small-signal model parameters; $R_i,R_o$; $A_{v,oc}$ and loaded $A_v$.
Approach. Use the given 1mA design current directly with $V_{BE}=0.7\text{V}$ to place the three DC node voltages, then build the standard hybrid-$\pi$ model from $I,\beta,V_A,V_T$ and read off resistances/gains from the CE topology.
Part (a) — DC node voltages. With $I_E\approx I_C=1\text{mA}$ flowing from the emitter into $R_E$ toward $-10\text{V}$:
$$V_E=-10\text{V}+I_ER_E=-10+(1\text{mA})(5\text{k}\Omega)=\boxed{-5.0\text{ V}}$$
$$V_B=V_E+V_{BE}=-5.0+0.7=\boxed{-4.3\text{ V}}$$
$$V_C=+10\text{V}-I_CR_C=10-(1\text{mA})(5\text{k}\Omega)=\boxed{5.0\text{ V}}$$
($V_{CE}=V_C-V_E=10\text{V}$, comfortably in the active region.)
Fig. Q4-b — Hybrid-$\pi$ small-signal model. $R_i$ looks into the base node ($R_B\|r_\pi$); $R_o$ and $A_v$ are read off $r_o\|R_C$ (open-circuit) or $r_o\|R_C\|R_L$ (loaded).
Part (c) — input/output resistance. The bias resistor $R_B$ appears directly in parallel with $r_\pi$ at the base (both seen looking in from $R_s$); at the collector, $r_o$ appears in parallel with $R_C$. Using the extracted $R_B\approx100\text{k}\Omega$:
$$R_i=R_B\|r_\pi=\frac{(100\text{k})(2.5\text{k})}{102.5\text{k}}=\boxed{2.44\text{ k}\Omega}$$
$$R_o=R_C\|r_o=\frac{(5\text{k})(100\text{k})}{105\text{k}}=\boxed{4.76\text{ k}\Omega}$$
Part (d) — gains. Open circuit (no $R_L$):
$$A_{v,oc}=-g_m(R_C\|r_o)=-(40\text{mA/V})(4.76\text{k}\Omega)=\boxed{-190\text{ V/V}}$$
Loaded ($R_L=5\text{k}\Omega$ added in parallel):
$$R_C\|r_o\|R_L=\frac{1}{\frac1{5\text{k}}+\frac1{100\text{k}}+\frac1{5\text{k}}}=2.44\text{k}\Omega$$
$$A_{v,L}=-g_m(2.44\text{k}\Omega)=-(40\text{mA/V})(2.44\text{k}\Omega)=\boxed{-97.6\text{ V/V}}$$
Adding the equal-valued $R_L$ very nearly halves the swing, since $R_C\|R_L=2.5\text{k}\Omega$ dominates the parallel combination with the much larger $r_o$.
