Question 7 of 7: 4-Bit Binary-Weighted Current-Mirror DAC

Question 7: 4-Bit Binary-Weighted Current-Mirror DAC (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Diode-connected $Q_1$ (NMOS, $W/L=80/2=40$) sets the gate voltage for four mirror transistors $Q_2$–$Q_5$ ($W/L=$ 80/2, 40/2, 20/2, 10/2 $=$ 40, 20, 10, 5). Their drains are switched by digital inputs $a_3,a_2,a_1,a_0$ onto a summing line feeding an op-amp's inverting input; $V_{bias}$ sets the non-inverting input; $R_F$ is the feedback resistor.

Find. Circuit name/operation; $V_{GS,Q1}$ and $I_{D,Q2\text{-}Q5}$; $I_o$ and $V_o$ for all 16 input codes.

Approach. $Q_1$'s diode connection fixes a single $V_{GS}$ shared by all five gates; each mirror transistor's $(W/L)$ ratio to $Q_1$ sets its current in binary-weighted proportion (40:20:10:5 = 8:4:2:1). The switches steer selected currents onto a summing node held at virtual-ground $V_{bias}$ by the op-amp, and $R_F$ converts the total current to an output voltage.

1. Part (a) — name and operation. This is a binary-weighted current-steering (current-mirror) digital-to-analog converter. A single reference current is mirrored through transistors sized in a binary ratio (8:4:2:1), and each digital input bit either steers its transistor's current onto the summing node or diverts it away; the op-amp/$R_F$ stage then converts the resulting total current into a proportional output voltage.
2. Part (b) — $V_{GS}$ and mirror currents. $Q_1$ (diode-connected): $I_D=(k'/2)(W/L)_1(V_{GS}-V_t)^2$: $$V_{GS}=V_t+\sqrt{\frac{2I_D}{k'(W/L)_1}}=1+\sqrt{\frac{2(0.8\text{mA})}{(40\mu\text{A/V}^2)(40)}}=1+1.0=\boxed{2.00\text{ V}}$$ With the same $V_{GS}$ applied to every mirror transistor ($V_{OV}=1.0\text{V}$ for all): $$I_{Q2}=\tfrac12k'(W/L)_2V_{OV}^2=\tfrac12(40\mu)(40)(1)^2=\boxed{0.800\text{ mA}}$$ $$I_{Q3}=\tfrac12(40\mu)(20)(1)^2=\boxed{0.400\text{ mA}},\quad I_{Q4}=\tfrac12(40\mu)(10)(1)^2=\boxed{0.200\text{ mA}},\quad I_{Q5}=\tfrac12(40\mu)(5)(1)^2=\boxed{0.100\text{ mA}}$$ These follow the intended 8:4:2:1 binary weighting relative to the $0.1\text{mA}$ LSB ($Q_5\to a_0$, $Q_4\to a_1$, $Q_3\to a_2$, $Q_2\to a_3$).
3. Part (c) — $I_o$ and full DAC table. With all switches to $V_{DD}$ (all bits high, all currents steered onto the summing line): $$I_{o,\max}=I_{Q2}+I_{Q3}+I_{Q4}+I_{Q5}=0.8+0.4+0.2+0.1=\boxed{1.5\text{ mA}}$$ For a general 4-bit code $N=8a_3+4a_2+2a_1+a_0$, $I_o=0.1\text{mA}\times N$. The op-amp forces its inverting input to $V_{bias}=2\text{V}$ (virtual short, zero bias current), and since no current flows into the op-amp input, all of $I_o$ is supplied through $R_F$ from the output: $$V_o=V_{bias}+I_oR_F=2\text{V}+(0.1\text{mA}\times N)(1\text{k}\Omega)=\boxed{2.0+0.1N\ \text{(V)}}$$

4. Part (d) — limitations. (i) Accuracy depends on precise $(W/L)$ ratio matching across four device sizes spanning a $8{:}1$ range — process gradients and edge effects distort the smallest ($Q_5$) device most, degrading INL/DNL and risking non-monotonicity. (ii) Fixed 4-bit resolution ($1/16$ of full scale per LSB). (iii) Switching transients and parasitic capacitance at the summing node limit settling time / conversion speed. (iv) All mirror $V_t$'s must match $Q_1$'s (temperature and process sensitive) or the binary weighting drifts. (v) Full-scale range is fixed by $R_F$ and the reference current, not independently adjustable without changing bias.