Question 1 of 7: Diode Limiter and Precision Rectifier
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Comp-A1, Electronics — National Exams, May 2014. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource). Unless stated otherwise, diode drops $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters/rectifiers, MOSFET/BJT small-signal amplifiers, active loads and current mirrors, active-RC filters, BJT switches, RTL logic, CMOS inverter design, RC oscillators, ring oscillators, ADC/DAC) — the single reference text covering every question on this paper.
Question 1: Diode Limiter and Precision Rectifier (20 marks)
Check — adopted circuit reading. The source's own extraction flags Figure 1 as "drawn in an unconventional and potentially confusing manner" and suggests the intended topology has $V_i$ driving a divider formed by $R_3,R_1$. Read literally, the extracted wiring (D1 bridging the same two nodes as R2, with the far node only ever "measured") leaves that far node with no return path for any diode current — not a solvable circuit. The engineering-sensible reading that uses every given component (R3, R1, R2, D1) in a single well-posed node is adopted here: $V_i(t)\xrightarrow{R_3}$ node $V_o$; $R_1$ shunts $V_o$ to ground (the divider the note describes); $R_2$ in series with $D_1$ (anode toward $V_o$) is a second shunt path to ground, providing a soft positive-side clamp. Figure 2's own R2/D2 pairing is read as the standard precision (active) inverting half-wave rectifier: R2 feeds back from the FINAL output $V_o$ to the inverting input (not from the raw op-amp output stage as one extracted phrase suggests), which is the only wiring that gives the circuit its well-known diode-drop-free behaviour asked for in part (d).
Find. $V_o(t)$ for both figures (peak values, key times), peak reverse voltage across $D_1$ (Fig.1), peak power dissipated in $D_1$ (Fig.1), and the operating-region transitions of both diodes in Fig.2.
Fig. Q1-a — $V_i(t)$ (blue, ±10V triangle) and $V_o(t)$ (orange). $V_o$ tracks $V_i/2$ (unclamped divider) whenever $V_i\lt1.4\text{V}$, then bends onto a shallower slope once $D_1$ conducts, flattening to $+4.14\text{V}$ at the positive peak. The negative half is unaffected (reaches $-5\text{V}$, the full divider value).
Approach. Fig.1(a-c): with $D_1$ off, $V_o$ is a plain $R_1/(R_1+R_3)$ divider of $V_i$; once that divider output would exceed $V_D=0.7\text{V}$, $D_1$ turns on and a full node equation (source, $R_1$, and the $R_2$-$D_1$ clamp branch) gives the soft-clamped region. Fig.2(d): recognise the classic precision inverting half-wave rectifier — the op-amp's negative feedback (through R2 from the final output) forces the diode drop out of the result entirely, giving an ideal rectified replica.
Fig.1 — turn-on threshold and unclamped region. With $D_1$ off, node $V_o$ is a simple divider: $V_o=V_i\cdot\dfrac{R_1}{R_1+R_3}=\dfrac{V_i}{2}$. This holds while $V_o\le V_D=0.7\text{V}$, i.e. while $V_i\le 1.4\text{V}$:
$$V_i^{th}=V_D\cdot\frac{R_1+R_3}{R_1}=0.7\times\frac{2000}{1000}=\boxed{1.4\text{ V}}$$
At the negative peak $V_i=-10\text{V}$ (always unclamped, single diode only clamps the positive side): $V_o=-10/2=\boxed{-5.0\text{ V (trough, unclipped)}}$.
Fig.1 — clamped region ($V_i>1.4\text{V}$). KCL at $V_o$ with $D_1$ conducting ($V_D=0.7\text{V}$ drop across the $R_2$-$D_1$ branch):
$$\frac{V_i-V_o}{R_3}=\frac{V_o}{R_1}+\frac{V_o-V_D}{R_2}\ \Rightarrow\ V_o=\frac{V_i/R_3+V_D/R_2}{1/R_3+1/R_1+1/R_2}=\frac{2V_i+0.7}{5}$$
At the positive peak $V_i=+10\text{V}$: $V_o=\dfrac{2(10)+0.7}{5}=\boxed{+4.14\text{ V (peak, soft-clamped)}}$.
Fig.1(b) — peak reverse voltage across $D_1$. While $D_1$ is off, no current flows in the $R_2$-$D_1$ branch, so there is no drop across $R_2$ and the diode sees the full node voltage: $V_{D_1}=V_o$. The most negative $V_o$ (at the $V_i=-10\text{V}$ trough) sets the worst case:
$$|V_{D_1}|_{\text{reverse, peak}}=|-5.0\text{ V}|=\boxed{5.0\text{ V}}$$
Fig.1(c) — peak power in $D_1$. Peak conduction current occurs at $V_i=+10\text{V}$ ($V_o=4.14\text{V}$):
$$I_{D_1,\text{pk}}=\frac{V_o-V_D}{R_2}=\frac{4.14-0.7}{2000}=1.72\text{ mA}$$
$$P_{D_1,\text{pk}}=I_{D_1,\text{pk}}\cdot V_D=(1.72\text{mA})(0.7\text{V})=\boxed{1.20\text{ mW}}$$
Fig.2(d) — precision rectifier behaviour. For $V_i\ge0$: the inverting stage needs its own output to swing negative to sink the $R_1$ current; $D_1$ (anode at the op-amp's raw output, now negative) is reverse biased, isolating $V_o$, which the (assumed) output load holds at $0\text{V}$; simultaneously $D_2$'s own threshold is not reached in this direction, so it plays no role. $$V_o=0\text{ V for }V_i\ge0$$
For $V_i\lt0$: the op-amp drives its raw output positive, forward-biasing $D_1$ and closing the loop through $R_2$ from $V_o$ itself back to the virtual ground — because the feedback senses $V_o$ directly (not the pre-diode node), the loop's high gain forces the ideal relation regardless of the $0.7\text{V}$ drop across $D_1$:
$$V_o=-V_i\cdot\frac{R_2}{R_1}=-V_i\ \text{(since }R_1=R_2\text{)}$$
$D_2$ only serves to prevent the op-amp's raw output from swinging uselessly negative during the $V_i\ge0$ half. With $V_i=10\sin(2\pi\cdot60t)$: $$V_o(t)=\boxed{10|\sin(2\pi\cdot60t)|\text{ restricted to }V_i\lt0\text{ half}}$$
i.e. $V_o=0$ for $0\lt t\lt T/2$ and $V_o$ rises to a peak of $+10\text{V}$ at $t=3T/4$ (where $T=1/60\text{s}=16.67\text{ms}$), falling back to $0$ at $t=T$, repeating every period.
Fig. Q1-d — $V_o(t)$ is exactly $0$ while $V_i\ge0$, then follows $-V_i$ (a mirrored, ideal, diode-drop-free replica) while $V_i\lt0$, peaking at $+10\text{V}$ at $t=12.5\text{ms}$.
