Question 7 of 7: Dual-Slope Integrating ADC and Weighted-Resistor DAC

Question 7: Dual-Slope Integrating ADC and Weighted-Resistor DAC (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Fig.10: op-amp integrator ($R$, $C$), switch selects $V_a$ (unknown, negative) or $V_{ref}$ (positive), $V_o(0)=0$. Fig.11: 4-bit binary-weighted-resistor summing DAC, feedback $R_f$, branches $S_a$–$S_d$ switching between $+5\text{V}$ and ground.

Find. $V_o(t)$ during both integrator phases, $T_2$ in terms of $T_1$, the counter relation $n_x(n_{ref})$, voltage resolution, and the DAC output expression + MSB identification.

Approach. Phase 1 is a plain Miller integration of the (negative) unknown $V_a$ over the fixed time $T_1$; phase 2 discharges that result at the fixed rate set by $V_{ref}$, and the ratio $T_2/T_1$ — hence the ratio of counter values — is independent of $R$, $C$, and the clock period, which is the entire point of dual-slope conversion.

1. Part (a) — integrating $V_a$. Standard inverting integrator, $V_o(0)=0$: $$V_o(t)=-\frac{1}{RC}\int_0^tV_a\,d\tau=\boxed{-\frac{V_a}{RC}\,t\quad(0\le t\le T_1)}$$ Since $V_a\lt0$ (given), $V_o(t)$ is a positive-going ramp, reaching $V_o(T_1)=-V_aT_1/RC$ at the end of phase 1.
2. Part (b) — discharge time $T_2$. From $t=T_1$, the switch feeds $+V_{ref}$, so $V_o$ ramps back down at rate $V_{ref}/RC$: $$V_o(t)=V_o(T_1)-\frac{V_{ref}}{RC}(t-T_1)$$ Setting $V_o(T_1+T_2)=0$: $$T_2=\frac{V_o(T_1)\cdot RC}{V_{ref}}=\boxed{\dfrac{|V_a|\,T_1}{V_{ref}}}$$
3. Part (c) — counter relation. Counting the same clock during both phases, $T_1=n_{ref}T_{clk}$ and $T_2=n_xT_{clk}$: $$n_x=\frac{T_2}{T_{clk}}=\frac{|V_a|}{V_{ref}}\cdot\frac{T_1}{T_{clk}}=\boxed{n_{ref}\cdot\dfrac{|V_a|}{V_{ref}}}$$ Notably $R$, $C$, and the clock period all cancel — the count ratio depends only on the voltage ratio, which is why dual-slope ADCs are insensitive to component drift.
4. Part (d) — voltage resolution. Each unit change in $n_x$ resolves: $$\Delta V_a=\frac{V_{ref}}{n_{ref}}=\frac{10\text{V}}{256}=\boxed{39.1\text{ mV per LSB}}$$
5. Part (e) — weighted-resistor DAC. Standard inverting summing amplifier, each branch contributing $-R_f(V_{branch}/R_{branch})$ when its switch selects $+5\text{V}$ (0 when grounded): $$V_o=-R_f\left(\frac{5S_a}{10\text{k}}+\frac{5S_b}{20\text{k}}+\frac{5S_c}{40\text{k}}+\frac{5S_d}{80\text{k}}\right)=\boxed{-\dfrac{5R_f}{10\text{k}\Omega}\left(S_a+\dfrac{S_b}{2}+\dfrac{S_c}{4}+\dfrac{S_d}{8}\right)}$$ where $S_x\in\{0,1\}$. $S_a$ (smallest resistance, $10\text{k}\Omega$) contributes the LARGEST weighted term ($8\times$ that of $S_d$), so $$\boxed{S_a=\text{MSB},\ S_d=\text{LSB}}$$