Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Comp-A1, Electronics — National Exams, May 2014. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource). Unless stated otherwise, diode drops $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters/rectifiers, MOSFET/BJT small-signal amplifiers, active loads and current mirrors, active-RC filters, BJT switches, RTL logic, CMOS inverter design, RC oscillators, ring oscillators, ADC/DAC) — the single reference text covering every question on this paper.
Question 4: BJT Inverter and RTL NOR Gate (20 marks)
Find. Active/saturation thresholds for $Q_1$ (Fig.5), small-signal gain, and the NOR-gate output states (Fig.6).
Approach. Fig.5 is a classic single-transistor switch: sweep $V_i$ through cutoff→active→saturation using $I_B=(V_i-V_{be})/R_B$, $I_C=\beta I_B$, $V_o=V_{CC}-I_CR_C$, capped at $V_{ce,sat}$. Fig.6 tests whether each input drives its own transistor into saturation, which is the logic-defining behaviour of an RTL gate.
Part (a) — onset of active region and $V_o$ expression. $Q_1$ is off (cutoff, $V_o=V_{CC}=5\text{V}$) while $V_i\lt V_{be}$. It becomes active the instant
$$V_i=\boxed{0.7\text{ V (onset of active region)}}$$
For $V_i\gt0.7\text{V}$ (still active), $I_B=(V_i-0.7)/R_B$, $I_C=\beta I_B$:
$$V_o=V_{CC}-\beta\frac{V_i-0.7}{R_B}R_C=\boxed{5-100(V_i-0.7)\text{ V}}$$
Part (b) — onset of saturation. Saturation begins once $V_o$ reaches $V_{ce,sat}=0.2\text{V}$:
$$0.2=5-100(V_i-0.7)\ \Rightarrow\ V_i=0.7+\frac{5-0.2}{100}=\boxed{0.748\text{ V}}$$
(the active region for this switch spans only $0.7\text{V}\lt V_i\lt0.748\text{V}$ — typical of a BJT used as a digital switch.)
Part (c) — small-signal gain at $I_C=1\text{mA}$. $$g_m=\frac{I_C}{V_T}=\frac{1\text{mA}}{25\text{mV}}=40\text{ mA/V}\qquad r_\pi=\frac{\beta}{g_m}=\frac{100}{40}=2.5\text{k}\Omega$$
Intrinsic stage gain (collector node only): $A_{v,\text{intrinsic}}=-g_mR_C=-(40)(1)=\boxed{-40\text{ V/V}}$.
Including the $R_B$-$r_\pi$ input divider (since $V_i$ is defined at the source, ahead of $R_B$):
$$A_v=-g_mR_C\cdot\frac{r_\pi}{r_\pi+R_B}=-40\times\frac{2.5}{3.5}=\boxed{-28.6\text{ V/V}}$$
Part (d) — RTL NOR, $V_A=V_B=0\text{V}$. Both base voltages are below $V_{be}=0.7\text{V}$, so both $Q_A,Q_B$ are OFF (cutoff): $I_C=0$ for both, no drop across $R_C$:
$$V_o=V_{CC}=\boxed{3.0\text{ V (both transistors OFF)}}$$
Part (e) — $V_A$ or $V_B=3\text{V}$. Whichever input is HIGH drives its transistor's base current hard: $I_B=(3-0.7)/450=5.11\text{mA}$, giving an unclamped $I_C=\beta I_B=511\text{mA}$ — far beyond what $R_C$ can support (saturation needs only $I_C=(3-0.2)/640=4.38\text{mA}$), so that transistor is driven deep into SATURATION:
$$V_o=V_{ce,sat}=\boxed{0.2\text{ V (at least one transistor SATURATED)}}$$
This confirms NOR behaviour: any HIGH input pulls the shared collector node low.