Question 6 of 7: CMOS Inverter Sizing and Ring Oscillator
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Comp-A1, Electronics — National Exams, May 2014. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource). Unless stated otherwise, diode drops $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters/rectifiers, MOSFET/BJT small-signal amplifiers, active loads and current mirrors, active-RC filters, BJT switches, RTL logic, CMOS inverter design, RC oscillators, ring oscillators, ADC/DAC) — the single reference text covering every question on this paper.
Question 6: CMOS Inverter Sizing and Ring Oscillator (20 marks)
Given. Fig.8: CMOS inverter, $V_{DD}=5\text{V}$. Fig.9: 5-inverter ring oscillator (odd number, one loop of inverting stages provides self-sustaining oscillation).
Given data
Quantity
Value
$k_n'$
$50\mu\text{A/V}^2$
$k_p'$
$20\mu\text{A/V}^2$
$V_{tn}=|V_{tp}|$
$1\text{V}$
$C_{ox}$
$1\text{fF}/\mu\text{m}^2$
Min gate length $L$
$1\mu\text{m}$
$t_p$ (part d, given)
$0.5\text{ns}$
Find. $(W/L)_n,(W/L)_p$ for symmetry, propagation delay estimate, waveform sketch of all 5 ring-oscillator nodes, and oscillation frequency.
Approach. Symmetric switching needs $k_n(W/L)_n=k_p(W/L)_p$ (matched pull-up/pull-down); propagation delay uses the standard $0.69R_{on}C_L$ estimate with $R_{on}$ from the large-signal on-resistance approximation; the ring oscillator's period is the classic $2Nt_p$ result for $N$ odd inverters.
Part (a) — symmetric sizing. With $L_n=L_p=1\mu\text{m}$ (minimum), symmetry requires $k_n'(W_n/L_n)=k_p'(W_p/L_p)$:
$$\frac{W_p}{W_n}=\frac{k_n'}{k_p'}=\frac{50}{20}=2.5$$
Choosing the minimum practical $W_n=1\mu\text{m}$: $$\boxed{(W/L)_n=1/1,\ (W/L)_p=2.5/1}$$
Part (b) — propagation delay (gate-oxide capacitance only). Load = gate capacitance of the next identical inverter:
$$C_L=C_{ox}(W_nL_n+W_pL_p)=1\text{fF}/\mu m^2\times(1+2.5)\mu m^2=\boxed{3.5\text{ fF}}$$
Estimate on-resistance (large-$V_{GS}$ approximation) for each device, using $k_n=k_n'(W/L)_n=50\mu A/V^2$, $k_p=k_p'(W/L)_p=20\times2.5=50\mu A/V^2$ (equal by the symmetric-sizing design):
$$R_{on,n}=R_{on,p}=\frac{1}{k(V_{DD}-V_t)}=\frac{1}{(50\mu A/V^2)(5-1)}=5.0\text{ k}\Omega$$
$$t_p=0.69R_{on}C_L=0.69(5.0\text{k}\Omega)(3.5\text{fF})=\boxed{12.1\text{ ps (both edges, by design symmetry)}}$$
Part (c) — ring-oscillator node waveforms. With node 1 transitioning LOW→HIGH at $t=0$, each subsequent node inverts the previous, delayed by one inverter's $t_p$: node $k$'s transition trails node $(k-1)$'s by exactly $t_p$. The loop's own inversion (5 inverters = net inversion) means node 1 itself must flip back low at $t=5t_p$, and the whole pattern repeats after $2\times5\times t_p=10t_p$ — that repeat interval is "one full period."
Part (d) — oscillation frequency ($t_p=0.5\text{ns}$ given). $$f=\frac{1}{2Nt_p}=\frac{1}{2(5)(0.5\text{ns})}=\boxed{200\text{ MHz}}$$
Fig. Q6-c — All 5 ring-oscillator nodes over one full period ($10t_p$). Node1 goes low→high at $t=0$ (as given); each following node repeats the transition, delayed by one more $t_p$; node1 itself flips back low at $t=5t_p$ (closing the ring's net inversion), and the pattern fully repeats at $t=10t_p$.
