Diode Limiter/Rectifier and Clamper: 98-Comp-A1, December 2015, Q1

Question 1: Diode Limiter/Rectifier and Clamper (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. $V_i(t)=5\sin(2\pi t)$ V (peak $5\text{V}$) in both figures; $R_1=50\,\Omega$, $C_1=1\,\mu\text{F}$; Fig.1 adds a series $V_1=5\text{V}$ bias battery ahead of $D_1$; $V_D=0.7\text{V}$.

Given data
Quantity	Value
$V_i(t)$	$5\sin(2\pi t)$ V, both figures
$V_1$ (Fig.1 series bias)	$5\text{V}$
$R_1$	$50\,\Omega$
$C_1$	$1\,\mu\text{F}$
$V_D$ (diode)	$0.7\text{V}$

Find. Fig.1: $V_i,V_o$ waveforms with peaks; $V_{o,\max},V_{o,\min}$; peak current in $R_1$. Fig.2: steady-state $V_o(t)$ with peak voltages labelled.

Fig. Q1(a) — Fig.1. The series $5\text{V}$ battery shifts the effective drive into $D_1$ up to $V_1+V_i(t)=5+5\sin(2\pi t)$, which never goes negative (0 to 10V). Since $R_1C_1=50\,\mu\text{s}$ is four orders of magnitude shorter than the 1s period, $C_1$ tracks essentially instantaneously: $V_o$ follows $(V_1+V_i)-V_D$ whenever that is positive, and collapses to $\approx0$ within the brief window it is not.

Approach. Fig.1: write KCL at the output node while $D_1$ conducts ($V_o=V_1+V_i(t)-V_D$ exactly, since the constant-drop model pins that relation); check the diode stays forward biased (current $\approx V_o/R_1>0$) for all but a brief trough window, because $R_1$'s discharge demand vastly exceeds $C_1$'s tiny differentiation current at this frequency. Fig.2: recognise the series-$C_1$/shunt-$D_1$/shunt-$R_1$ arrangement as the classic negative clamper — in the idealised analysis (feedback resistor's discharge assumed negligible over one cycle, the standard textbook clamper assumption) the capacitor settles to a level that clamps the waveform's positive peak at $+V_D$.

Part (a)/(b) — Fig.1 $V_o$ waveform and its extremes. The effective drive into the diode is $V_1+V_i(t)=5+5\sin(2\pi t)$, ranging over $[0,10]\text{V}$ — never negative. While $D_1$ conducts, $$V_o(t)=V_1+V_i(t)-V_D=4.3+5\sin(2\pi t)$$ so the crest gives the maximum output directly: $$V_{o,\max}=(5+5)-0.7=\boxed{9.3\text{ V}}$$ $D_1$ only cuts off when $V_1+V_i(t)
Part (c) — peak current in $R_1$. The peak node voltage is $V_{o,\max}=9.3\text{V}$, and since $R_1$ is the only element carrying that current away at the crest, $$I_{R_1,\text{pk}}=\frac{V_{o,\max}}{R_1}=\frac{9.3}{50}=\boxed{186\text{ mA}}$$
Part (d) — Fig.2 ideal clamper. With the standard clamper assumption ($R_1C_1$ effectively long enough to hold the capacitor's charge across a cycle, the textbook idealisation used to sketch the waveform — see the check note below), $C_1$ charges to $V_C=V_{i,\text{pk}}-V_D=5-0.7=4.3\text{V}$ so that $D_1$ only has to top it up right at the crest. The output tracks the input shifted down by that same amount: $$V_o(t)=V_i(t)-V_C=5\sin(2\pi t)-4.3$$ $$V_{o,\max}=5-4.3=\boxed{+0.7\text{ V}}\qquad V_{o,\min}=-5-4.3=\boxed{-9.3\text{ V}}$$ $D_1$ conducts only in the brief instant the waveform tries to exceed $+0.7\text{V}$ (replenishing $C_1$); it is reverse biased everywhere else.

Fig. Q1(d) — Fig.2 ideal negative clamper. Positive crest clamped at $+0.7\text{V}$, waveform shifted down so the trough reaches $-9.3\text{V}$.

Check — ideal-clamper assumption for Fig.2. With the literal component values ($R_1C_1=50\,\mu\text{s}$ against a 1s period), the capacitor would actually discharge through $R_1$ almost completely between diode pulses, placing the circuit deep in the "differentiator" regime rather than acting as a true DC-restoring clamper (the sketch would instead be a tiny millivolt-level spike, not a shifted sine). This is clearly not the intended teaching point of a "sketch the clamped output, label peak voltages" question, so the answer above adopts the standard idealised clamper analysis ($R_1C_1\gg T$, the assumption always used to introduce this topology) and flags the literal component values as an inconsistency in the source rather than re-deriving a differentiator response.

Final Results — Question 1
Quantity	Value
Fig.1 $V_{o,\max}$	$9.3\text{ V}$
Fig.1 $V_{o,\min}$	$\approx0\text{ V}$
Fig.1 peak $I_{R_1}$	$186\text{ mA}$
Fig.2 $V_o(t)$	$5\sin(2\pi t)-4.3$ V (ideal clamper)
Fig.2 $V_{o,\max},V_{o,\min}$	$+0.7\text{V},\ -9.3\text{V}$

Topic: Diode limiters, biased rectifiers, and clampers.

Key relations: Constant-drop diode model $V_D=0.7\text{V}$; forward-conduction pins $V_o=V_{\text{source}}-V_D$; a clamper's DC restoration requires $R\,C\gg T$ so the capacitor voltage barely decays between recharging pulses.

Why this works: A series battery ahead of a diode simply shifts the effective threshold the source must cross (Fig.1); a series capacitor ahead of a shunt diode instead lets the capacitor's DC level float to whatever value keeps the diode just at the edge of conduction once per cycle (Fig.2) — the two topologies are duals of each other (one clips relative to ground, the other clips relative to a floating, self-adjusting reference).

Common pitfall: Forgetting to check that the RC time constant is long enough to justify the ideal clamper/peak-detector approximation — with a short time constant the circuit instead behaves like a high-pass filter/differentiator, a qualitatively different response.

Source: Sedra & Smith, Microelectronic Circuits, Diode Circuits — Limiting and Clamping Circuits.

Question 1 of 7: Diode Limiter/Rectifier and Clamper

Question 1: Diode Limiter/Rectifier and Clamper (20 marks)