Question 6 of 7: CMOS Inverter Sizing/Delay and a Clocked Cross-Coupled Latch

Question 6: CMOS Inverter Sizing/Delay and a Clocked Cross-Coupled Latch (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. $k_n'=50\,\mu\text{A/V}^2$, $k_p'=20\,\mu\text{A/V}^2$, $V_{tn}=|V_{tp}|=1\text{V}$, $C_{ox}=1\text{fF}/\mu\text{m}^2$, $V_{DD}=5\text{V}$, $L_{\min}=1\,\mu\text{m}$; $C_{gd}=0.5\text{fF}/\mu\text{m}$ (per transistor width), $C_{db}=10\text{fF}$ (each of $Q_N,Q_P$), wiring $C_w=5\text{fF}$.

Find. $(W/L)_n,(W/L)_p$ for a symmetric VTC; propagation delay driving an identical inverter; the $X,Y$ truth table for Fig.8; minimum $(W/L)$ for $Q_5,Q_6$.

Approach. Symmetric switching requires matched drive strength $k_n'(W/L)_n=k_p'(W/L)_p$; delay follows from the (matched, so equal) saturation currents charging/discharging the lumped load capacitance through roughly half a $V_{DD}$ swing. Fig.8's truth table follows from tracing which pull-down/pull-up wins the contest at each write node when the pass gates are enabled; the $Q_5/Q_6$ sizing repeats the same drive-matching idea, now pitting the pass transistor against the OPPOSING cross-coupled PMOS.

1. Part (a) — symmetric sizing. Symmetric VTC (switching threshold at $V_{DD}/2$) needs equal drive strength: $$k_n'\left(\frac{W}{L}\right)_n=k_p'\left(\frac{W}{L}\right)_p$$ Choosing $Q_N$ at minimum size, $(W/L)_n=1/1=1$ ($W_n=1\,\mu\text{m}$): $$\left(\frac{W}{L}\right)_p=\frac{k_n'}{k_p'}\left(\frac{W}{L}\right)_n=\frac{50}{20}(1)=\boxed{2.5}\ \ (W_p=2.5\,\mu\text{m},\ L_p=1\,\mu\text{m})$$
2. Part (b) — propagation delay. Total load capacitance at $V_o$: self-loading ($C_{db,n}+C_{db,p}$), Miller-doubled overlap caps ($2C_{gd,n}+2C_{gd,p}$), wiring, and the NEXT (identical) stage's gate capacitance ($C_{ox}W_nL_n+C_{ox}W_pL_p$): $$C_{gd,n}=0.5(1)=0.5\text{fF},\quad C_{gd,p}=0.5(2.5)=1.25\text{fF}$$ $$C_L=\underbrace{2(10)}_{C_{db}}+\underbrace{2(0.5+1.25)}_{\text{Miller }C_{gd}}+\underbrace{5}_{\text{wiring}}+\underbrace{[1(1)+1(2.5)]}_{\text{next-stage gates}}=20+3.5+5+3.5=\boxed{32\text{ fF}}$$ Saturation drive current at $V_{GS}=V_{DD}$ (equal for both by the symmetric design): $$I_{DSAT}=\tfrac12 k_n'(W/L)_n(V_{DD}-V_{tn})^2=\tfrac12(50\mu)(1)(4)^2=400\,\mu\text{A}\ (=I_{DSAT,p}\text{ too})$$ Using the standard equivalent-resistance delay estimate $R_{eq}\approx\tfrac34\,V_{DD}/I_{DSAT}$ and $t_p=0.69R_{eq}C_L$: $$R_{eq}=\tfrac34(5/400\mu)=9.375\text{k}\Omega\qquad t_{pHL}=t_{pLH}=0.69(9.375\text{k})(32\text{fF})=207\text{ ps}$$ $$t_p=\boxed{207\text{ ps}}\ \text{(symmetric by design, so }t_{pHL}=t_{pLH})$$

3. Part (c) — Fig.8 truth table. $Q_1(N)/Q_2(P)$ cross-coupled from $Y$ drive $X$; $Q_3(N)/Q_4(P)$ cross-coupled from $X$ drive $Y$ — a bistable latch. $Q_5$ (gated by $\phi$) writes $A$ onto $X$; $Q_6$ writes $B$ onto $Y$.

   $\phi$	$A$	$B$	$X$	$Y$	Mode
   0	—	—	$X_{\text{prev}}$	$Y_{\text{prev}}$	Hold (latched, $Q_5,Q_6$ off)
   1	0	1	0	1	Write "0" (consistent with the cross-coupled pair's own preference)
   1	1	0	1	0	Write "1" (consistent)
   1	0	0	0	0	Contention — both pass gates fight the cross-coupled feedback; resolved by pass-gate strength (part d)
   1	1	1	1	1	Contention (same as above, opposite polarity)

   Normal (non-contending) write operation needs $B=\overline{A}$, matching the latch's own complementary equilibrium; $A=B$ forces both nodes to the same value against the cross-coupled inverters' natural preference, and the outcome then depends on which device wins — exactly the sizing constraint part (d) asks for.
4. Part (d) — minimum $(W/L)_5=(W/L)_6$. Worst case: writing $A=0$ while the OPPOSING PMOS $Q_2$ (gate fixed at $Y=0$ from the prior state) is trying to hold $X$ high. At the target $X=V_{DD}/2=2.5\text{V}$, both devices sit in TRIODE (check: $V_{GS}-V_{tn}=4\text{V}>V_{DS}=2.5\text{V}$ for $Q_5$; $V_{SG}-|V_{tp}|=4\text{V}>V_{SD}=2.5\text{V}$ for $Q_2$). Current balance (KCL at $X$, both devices share the identical triode bracket $[(4)(2.5)-2.5^2/2]=6.875$ since $V_{DD},V_{tn},|V_{tp}|$ are all symmetric about $V_{DD}/2$): $$k_p'\left(\frac{W}{L}\right)_{2}(6.875)=k_n'\left(\frac{W}{L}\right)_{5}(6.875)$$ $$\left(\frac{W}{L}\right)_5=\frac{k_p'}{k_n'}\left(\frac{W}{L}\right)_2=\frac{20}{50}(2.5)=\boxed{1.0}\ \ (\text{i.e. }W_5=W_6=1\,\mu\text{m},\ \text{same minimum size as }Q_N)$$ The identical triode bracket cancelling out is exactly the same $k_n'(W/L)=k_p'(W/L)$ matching condition as part (a) — no new inequality to solve.