Question 7 of 7: MOSFET Current-Steering (Binary-Weighted) DAC
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Comp-A1, Electronics — National Exams, December 2015. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource, per the standing "answer all M" rule). Unless stated otherwise, diode drops $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters/rectifiers/clampers, MOSFET/BJT small-signal amplifiers, active loads and current mirrors, active-RC filters, differential pairs with current-mirror loads, op-amp astable multivibrators, CMOS inverter design and delay, clocked cross-coupled latches, current-steering DACs) — the single reference text covering every question on this paper.
Find. Circuit name/operation; $I_{D1}$ (iterative); $I_o$ at full-scale and $V_o$ for every 4-bit code $A_{in}=0000..1111$; application limitations.
Approach. $Q_1$ (diode-connected) sets a reference gate voltage via a KVL loop through $R_B$ combined with its own saturation equation — solved by iteration since the equation is quadratic in $V_{GS}$. That gate voltage mirrors onto $Q_2$-$Q_5$, whose binary-weighted $W/L$ ratios scale the mirrored current into a binary-weighted current set; each bit's switch pair steers its current into $I_o$ or away, so $I_o=\sum a_i\,I_i$. The op-amp (virtual node held at $V_{bias}$) converts $I_o$ to a voltage via $R_F$.
Part (a) — identification. This is a binary-weighted current-steering digital-to-analog converter (DAC): a single reference current (set by $Q_1,R_B$) is mirrored into $2^n$-scaled current sources ($Q_2$-$Q_5$, ratios $8{:}4{:}2{:}1$), and each source's current is switched ("steered") by a differential pair into either the summing node $I_o$ (bit $=1$) or a dummy rail (bit $=0$). The op-amp transimpedance stage converts the resulting sum current into an output voltage proportional to the binary code.
Part (b) — $I_{D1}$ by iteration. KVL: $V_{DD}=I_{D1}R_B+V_{GS1}$, with $I_{D1}=\tfrac12k'(W/L)_{Q1}(V_{GS1}-V_t)^2=\tfrac12(40\mu)(40)(V_{GS1}-0.8)^2=800\mu(V_{GS1}-0.8)^2$. Starting from a guess $V_{GS1}=1.5\text{V}$ and iterating $V_{GS1}\leftarrow V_{DD}-I_{D1}R_B$ (under-relaxed for stability) converges to:
$$V_{GS1}=\boxed{1.282\text{ V}}\qquad I_{D1}=800\mu(1.282-0.8)^2=\boxed{185.9\,\mu\text{A}}$$
(equivalently, solving the quadratic $16(V_{GS1}-0.8)^2+V_{GS1}=5$ directly gives the same physical root, confirming the iteration.)
Fig. Q7(c) — DAC transfer characteristic. $V_o$ steps linearly with the 4-bit code $N$ (LSB step $=0.1162\text{V}$), from $1.000\text{V}$ ($N=0$) to $2.743\text{V}$ ($N=15$).
Part (c) — branch currents, full-scale $I_o$, and the $A_{in}$ table. Mirror ratio scales $I_{D1}$ directly (identical $V_{GS}$, so $I_i=I_{D1}\times(W/L)_i/(W/L)_{Q1}$):
$$I_{a_3}=185.9\mu\text{A}\ (\times8/8),\ \ I_{a_2}=93.0\mu\text{A}\ (\times4/8),\ \ I_{a_1}=46.5\mu\text{A}\ (\times2/8),\ \ I_{a_0}=23.2\mu\text{A}\ (\times1/8)$$
With $a_3$-$a_0$ all tied to $V_{DD}$ (code $1111$), every branch steers into $I_o$:
$$I_{o,\text{full-scale}}=185.9+93.0+46.5+23.2=\boxed{348.6\,\mu\text{A}}$$
The op-amp's virtual $-$ input sits at $V_{bias}$ (ideal, no input current), and $I_o$ is supplied through $R_F$ from $V_o$:
$$V_o=V_{bias}+I_oR_F$$
Applying this for every 4-bit code ($I_{LSB}=I_{a_0}=23.24\,\mu\text{A}$, $I_o=N\cdot I_{LSB}$, $N=8a_3+4a_2+2a_1+a_0$):
$N$
$a_3a_2a_1a_0$
$I_o\ (\mu\text{A})$
$V_o$ (V)
0
0000
0.00
1.000
1
0001
23.24
1.116
2
0010
46.47
1.232
3
0011
69.71
1.349
4
0100
92.95
1.465
5
0101
116.19
1.581
6
0110
139.42
1.697
7
0111
162.66
1.813
8
1000
185.90
1.930
9
1001
209.13
2.046
10
1010
232.37
2.162
11
1011
255.61
2.278
12
1100
278.85
2.394
13
1101
302.08
2.510
14
1110
325.32
2.627
15
1111
348.56
2.743
Part (d) — limitations. (i) Matching: binary-weighted current sources spanning $8{:}1$ (or more, for wider words) demand large-area MSB devices matched to small LSB devices — process gradients and random mismatch degrade both linearity (INL/DNL) and monotonicity, worst at major-code transitions (e.g. $0111\to1000$, where the $8\times$ MSB switches on as all smaller bits switch off — a large enough MSB error can make the DAC briefly non-monotonic). (ii) No channel-length modulation compensation: the analysis assumed ideal current mirroring; real devices' $V_{DS}$ differs slightly across codes (since $I_o$'s node voltage is pinned at $V_{bias}$ but the switch/mirror internal nodes are not identical), introducing gain error via finite $V_A$. (iii) Switching speed/glitches: the differential switch pairs take finite time to steer current, and unequal rise/fall through them causes code-dependent glitch energy at major transitions. (iv) Reference sensitivity: $I_{D1}$ (and hence every bit current) depends on $V_{DD}$, $V_t$, and $k'$, all of which vary with supply and temperature — there is no bandgap-style compensation here, so full-scale output drifts with process/temperature/supply. (v) Resolution limits: binary weighting practically caps around 8-10 bits before matching/area becomes prohibitive; higher-resolution DACs typically switch to segmented or R-2R architectures for exactly this reason.
Final Results — Question 7
Quantity
Value
Circuit name
Binary-weighted current-steering DAC
$V_{GS1}$ (iterated)
$1.282\text{ V}$
$I_{D1}$
$185.9\,\mu\text{A}$
$I_{o}$ (full scale, $N=15$)
$348.6\,\mu\text{A}$
$V_o$ range
$1.000\text{V}$ ($N{=}0$) to $2.743\text{V}$ ($N{=}15$)
