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98-Comp-A1 · May 2016

Question 1 of 7: Full-Wave Rectifier with Zener Shunt Regulator

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

98-Comp-A1, Electronics — National Exams, May 2016. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource, per the standing "answer all M" rule). Unless stated otherwise, diode drops $V_D=0.7\text{V}$.

Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters/rectifiers/zener regulators, MOSFET current-mirror biasing and CS amplifiers, active-RC filters with T-network feedback, BJT cascode differential pairs with Wilson current-mirror loads, RC-ladder (Wien-bridge type) sinusoidal oscillators, CMOS static/pass-transistor logic synthesis and sizing, switched-capacitor dual-slope integrators) — the single reference text covering every question on this paper.

Question 1: Full-Wave Rectifier with Zener Shunt Regulator (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. $V_1(t)=10\sin(2\pi t)\text{V}$, $V_2(t)=-10\sin(2\pi t)\text{V}$ (period $T=1\text{s}$); $D_1,D_2$ forward drop $V_D=0.7\text{V}$; $C_1=1\,\mu\text{F}$; $R_1=50\,\Omega$; $D_3$ zener breakdown $V_Z=5.1\text{V}$; no external load other than the $R_1$–$D_3$ branch.

Given data
QuantityValue
$V_1(t)$$10\sin(2\pi t)$ V
$V_2(t)$$-10\sin(2\pi t)$ V
$V_D$ ($D_1,D_2$)$0.7$ V
$C_1$$1\,\mu\text{F}$
$R_1$$50\,\Omega$
$V_Z$ ($D_3$)$5.1$ V

Find. $V_1,V_2,V_o$ and $V_C$ waveforms with peaks labelled; peak current in $R_1$; a suitable power rating for $D_3$.

Approach. $D_1$ conducts whenever $V_1$ exceeds $V_C+V_D$ (near $V_1$'s crest); $D_2$ conducts whenever $V_2$ exceeds $V_C+V_D$ (near $V_2$'s crest, i.e. $V_1$'s trough) — together they recharge $V_C$ twice per period, exactly like a center-tapped full-wave rectifier. Because $\tau=R_1C_1=50\,\mu\text{s}\ll T=1\text{s}$, $C_1$ could discharge far faster than either sine falls, so it never stores the crest. The conducting diode stays on while its source falls, and $V_C$ follows the higher of $V_1,V_2$ minus $V_D$. When both are below $V_Z+V_D=5.8\text{V}$, $V_C$ rests at the zener floor $V_Z=5.1\text{V}$, because there is no discharge path once $D_3$ stops conducting. So $V_C(t)=\max\big(|10\sin 2\pi t|-0.7,\ 5.1\big)$, and $D_3$ holds $V_o$ at $V_Z$ throughout.

  1. Part (a)/(b) — steady-state waveforms. $V_1$ and $V_2$ are $10\text{V}$-peak sines in anti-phase (period $1\text{s}$). $D_1$ turns on when $V_1$ reaches $V_Z+V_D=5.8\text{V}$, at $t_1=\sin^{-1}(0.58)/2\pi=0.0985\text{s}$. From then on $V_C(t)=V_1(t)-V_D$, rising to a peak at $t=0.25\text{s}$ of $$V_{C,\text{pk}}=10-0.7=\boxed{9.3\text{ V}}$$ After the crest, $D_1$ does not cut off. With $\tau=R_1C_1=50\,\mu\text{s}$, the capacitor would discharge through $R_1$ into $D_3$ far faster than $V_1$ falls, so $D_1$ stays forward-biased and $V_C$ tracks $V_1-V_D$ back down to $5.1\text{V}$ at $t=0.5-0.0985=0.4015\text{s}$. It then rests flat at $V_Z=5.1\text{V}$ (no discharge path once $D_3$ stops conducting) until $D_2$ takes over on the other half-cycle, from $0.5985$ to $0.9015\text{s}$, peaking at $9.3\text{V}$ at $t=0.75\text{s}$. So $V_C$ is a train of rectified sine-tops, $V_C(t)=\max(|V_1|-0.7,\,5.1)$, ranging from $5.1\text{V}$ to $9.3\text{V}$ at $2\text{Hz}$. Because $V_C\ge V_Z$ at every instant, $D_3$ holds the output at $$V_o(t)\approx V_Z=\boxed{5.1\text{ V (flat DC)}}$$ — the shunt-zener regulator removes the $1\text{Hz}$ ripple almost completely, which is the whole point of the topology.
  2. Part (c) — peak current in $R_1$. The worst-case (peak) drop across $R_1$ occurs the instant $V_C$ reaches its crest while $V_o$ is clamped at $V_Z$: $$I_{R_1,\text{pk}}=\frac{V_{C,\text{pk}}-V_Z}{R_1}=\frac{9.3-5.1}{50}=\boxed{84\text{ mA}}$$
  3. Part (d) — power rating for $D_3$. All of $I_{R_1,\text{pk}}$ flows through $D_3$ at that instant (no other load is given), so the worst-case instantaneous dissipation is $$P_{D_3,\text{pk}}=V_Z\cdot I_{R_1,\text{pk}}=5.1\times0.084=\boxed{428\text{ mW}}$$ The zener does not see only brief pulses. It conducts whenever $V_C>5.1\text{V}$, about $61\%$ of each cycle, so its average dissipation is substantial: $$P_{D_3,\text{avg}}=\frac{1}{T}\int_0^T V_Z\,\frac{\max(|V_1|-0.7-V_Z,\,0)}{R_1}\,dt\approx\boxed{0.17\text{ W}}$$ The $0.43\text{W}$ peak repeats twice per second, which is too slow for thermal averaging to help much, so size for the peak. A $0.5\text{W}$ zener is the bare minimum; a $1\text{W}$ device (about $2\times$ margin on the peak, allowing for temperature derating) is the sensible choice.
t (s) V 0 0.25 0.5 0.75 1.0 -10 0 5.1 +10 V1(t)=10sin(2πt) V2(t)=-10sin(2πt) Vo(t) (regulated)
Fig. Q1(a) — V1, V2 are 10V-amplitude anti-phase sources (like a center-tapped secondary); Vo is clamped by zener D3 to a flat 5.1V for essentially the whole cycle.
t (s) V 0 t1 0.25 t2 0.75 1.0 0 5.1 9.3 Vc(t)
Fig. Q1(b) — Vc tracks V1-0.7V (then V2-0.7V) up to the 9.3V peak while D1 (D2) conducts, then back down along the same sine (τ=R1C1=50µs ≪ T=1s, so the diode stays on as its source falls) to the 5.1V zener floor, where it rests until the other source exceeds 5.8V: Vc = max(|V1|-0.7, 5.1).
Final Results — Question 1
QuantityValue
$V_{C,\text{pk}}$$9.3$ V
$V_o$ (regulated)$\approx5.1$ V, flat
$V_C$ range$5.1$–$9.3$ V, $V_C=\max(|V_1|-0.7,\,5.1)$
$I_{R_1,\text{pk}}$$84$ mA
$P_{D_3}$ peak / average$428$ mW / $\approx170$ mW
$D_3$ rating$\ge0.5\text{ W}$ (peak), $1\text{ W}$ recommended
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