Question 2 of 7: PMOS Current-Mirror-Biased CS Amplifier
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Comp-A1, Electronics — National Exams, May 2016. Open-book, 3 hours; seven 20-mark questions, five to be marked (all seven answered below as a complete study resource, per the standing "answer all M" rule). Unless stated otherwise, diode drops $V_D=0.7\text{V}$.
Reference texts: Sedra & Smith, Microelectronic Circuits (diode limiters/rectifiers/zener regulators, MOSFET current-mirror biasing and CS amplifiers, active-RC filters with T-network feedback, BJT cascode differential pairs with Wilson current-mirror loads, RC-ladder (Wien-bridge type) sinusoidal oscillators, CMOS static/pass-transistor logic synthesis and sizing, switched-capacitor dual-slope integrators) — the single reference text covering every question on this paper.
Given. $V_{DD}=5\text{V}$; $k_n'=k_p'=1\text{ mA/V}^2$ (matched process, only one $k'$ given); $W/L=10$ for all three transistors; $|V_t|=1\text{V}$; $V_A=100\text{V}$; $\lambda=0$ in the square-law DC equation; target $I_{D,Q3}=0.5\text{mA}$.
Approach. $Q_3$ is diode-connected, so its own square-law equation plus $R$'s IV relation fixes $R$. $Q_2$ mirrors $Q_3$'s current 1:1 (same $V_{SG}$, same $W/L$) into $Q_1$'s drain, biasing $Q_1$ at the same $0.5\text{mA}$; the small-signal gain then follows from $Q_1$'s $g_{m1}$ driving the parallel combination of both transistors' output resistances.
Part (a) — solve for $R$. $Q_3$ diode-connected (assume $\lambda=0$): $I_{D3}=\tfrac12 k_p'(W/L)(V_{SG3}-|V_t|)^2$, so
$$V_{OV3}=\sqrt{\frac{2I_{D3}}{k_p'(W/L)}}=\sqrt{\frac{2(0.5\text{mA})}{(1\text{mA/V}^2)(10)}}=\sqrt{0.1}=0.3162\text{V}$$
$$V_{SG3}=V_{OV3}+|V_t|=0.3162+1=1.3162\text{V}$$
The node between $Q_3$'s drain and $R$ sits at $V_{DD}-V_{SG3}=5-1.3162=3.6838\text{V}$ above ground, and carries the same $I_{D3}$ into $R$:
$$R=\frac{V_{DD}-V_{SG3}}{I_{D3}}=\frac{3.6838}{0.5\text{mA}}=\boxed{7.37\text{ k}\Omega}$$
Part (b) — small-signal model. $Q_2$'s gate sits at the fixed DC bias set by the $Q_3$–$R$ reference (no signal reaches it, since $v_i$ only excites $Q_1$'s gate), so for small signals $Q_2$ collapses to its output resistance $r_{o2}$ from the AC-grounded $5\text{V}$ rail to $v_o$. $Q_1$ becomes the usual hybrid-$\pi$/T model: a dependent source $g_{m1}v_{gs1}$ ($v_{gs1}=v_i$, source grounded) in parallel with $r_{o1}$, both landing on node $v_o$, so $r_{o1}\parallel r_{o2}$ is the total load the current source drives.
Part (c) — AC gain. Both $Q_1$ and $Q_2$ carry $I_D=0.5\text{mA}$ (the mirror sets $I_{D1}=I_{D2}=I_{D3}$), so
$$g_{m1}=\sqrt{2k_n'(W/L)I_{D1}}=\sqrt{2(1\text{mA/V}^2)(10)(0.5\text{mA})}=\sqrt{10}\text{ mA/V}=3.162\text{ mA/V}$$
$$r_{o1}=r_{o2}=\frac{V_A}{I_D}=\frac{100}{0.5\text{mA}}=200\text{ k}\Omega$$
$$A_v=\frac{v_o}{v_i}=-g_{m1}\big(r_{o1}\parallel r_{o2}\big)=-(3.162\text{mA/V})(100\text{k}\Omega)=\boxed{-316\text{ V/V}}$$
Fig. Q2(b) — AC small-signal model: dependent source gm1·vgs1 (Q1, driven by vi at its gate) in parallel with ro1, feeding node vo, with the PMOS current-source load Q2 replaced by ro2 to the (AC-grounded) 5V rail; ro2 and ro1 both terminate at vo, in parallel.