Question 6 of 7: CMOS Logic Synthesis and Transistor Sizing

Question 6: CMOS Logic Synthesis and Transistor Sizing (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Target function $Y=\overline{AB(C+D)}$; minimum channel length $L=1\,\mu\text{m}$ throughout; reference (unit) inverter sizes $W_n=2\,\mu\text{m}$, $W_p=5\,\mu\text{m}$ (both $L=1\,\mu\text{m}$).

Find. (a) Pull-up/pull-down network topology; (b) transistor widths; (c) a pass-transistor-logic realization.

Approach. Build the NMOS pull-down network so it conducts (pulls $Y$ low) exactly when $f=AB(C+D)$ is true — series $A$, series $B$, then a parallel $C,D$ pair, all in series from $Y$ to ground. The PMOS pull-up network is the series–parallel dual of that graph (same literal gate signals; PMOS conducts on gate$=0$), so it conducts exactly when $f$ is false. Size each transistor for the worst-case (longest) series chain it can be part of, using $N\times$ the unit width for an $N$-deep series stack.

1. Part (a) — network synthesis. NMOS pull-down (conducts $\Leftrightarrow AB(C+D)$, pulling $Y$ low $\Leftrightarrow f=1\Rightarrow Y=0$): $$\text{PDN: }A\text{ (series)} - B\text{ (series)} - \big(C\parallel D\big)\text{, from }Y\text{ to GND}$$ PMOS pull-up is the dual graph (series$\leftrightarrow$parallel), same signals $A,B,C,D$ on the gates: $$\text{PUN: }A\parallel B\parallel\big(C\text{ (series) }D\big)\text{, from }V_{DD}\text{ to }Y$$ Check by De Morgan: PUN conducts $\Leftrightarrow A'+B'+C'D'=\overline{AB(C+D)}=\bar f$, so $Y=1$ exactly when $f=0$ — consistent with the PDN, and together they form a complete, non-floating static CMOS gate for every input combination.
2. Part (b) — sizing. NMOS: every one of $A,B,C,D$ can appear in a 3-deep worst-case series path ($A,B$ together with whichever of $C,D$ is on), so each is sized $3\times$ the unit NMOS: $$W_{n,A}=W_{n,B}=W_{n,C}=W_{n,D}=3\times2\,\mu\text{m}=\boxed{6\,\mu\text{m}}\ (L=1\,\mu\text{m})$$ PMOS: $A,B$ each stand alone (depth 1, no series partner) so need only the unit width; $C,D$ sit in a 2-deep series branch, so need $2\times$ the unit PMOS: $$W_{p,A}=W_{p,B}=1\times5\,\mu\text{m}=\boxed{5\,\mu\text{m}},\qquad W_{p,C}=W_{p,D}=2\times5\,\mu\text{m}=\boxed{10\,\mu\text{m}}\ (L=1\,\mu\text{m})$$
3. Part (c) — pass-transistor logic. Build $F=AB(C+D)$ directly with NMOS pass transistors, mirroring the same series/parallel topology as the PDN but passing a logic-1 (from $V_{DD}$) instead of pulling down: series $A,B$ (both must be high to pass the signal) into a parallel $C,D$ pass pair reaching node $F$. Because a pure NMOS pass network has no path to ground, something must define logic-0 when no path conducts: a weak (ratioed) pull-down to ground or, better, a complementary pass network or transmission gates. The NMOS pass path delivers only a degraded high, $V_{DD}-V_{tn}$ (series pass devices with their gates at $V_{DD}$ do not add further threshold drops), so a single static inverter then restores full-swing $Y=\bar F=\overline{AB(C+D)}$, matching part (a)'s function.