Question 7 of 7: Switched Dual-Slope Integrator/Comparator

Question 7: Switched Dual-Slope Integrator/Comparator (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Miller integrator with series $R$, feedback $C$; input switched $V_A$ (phase 1, $0\to T_1$) then $V_R$ (phase 2, $T_1\to T_2$); $V_A<0$, $V_R>0$; capacitor initially discharged ($V_x(0)=0$); comparator flips at $V_x=0$.

Find. (a) $V_x(t)$ sketch; (b) slope in each phase; (c) $T_2/T_1$; (d) limitations.

Approach. Integrate the (constant, piecewise) input in each phase: $V_x(t)=-\dfrac{1}{RC}\displaystyle\int V_{\text{in}}\,dt$. Phase 1 ramps $V_x$ up (since $V_A<0$); phase 2 ramps it back down (since $V_R>0$) until it re-crosses zero at $T_2$, which is exactly the classic dual-slope ADC principle (used in digital voltmeters) — $T_2-T_1$ encodes the unknown $V_A$ relative to the known reference $V_R$, independent of $R$ and $C$.

1. Part (b) — slopes. Miller integrator: $dV_x/dt=-V_{\text{in}}/(RC)$. $$\text{Phase 1 (}0\le t\le T_1\text{):}\quad \frac{dV_x}{dt}=-\frac{V_A}{RC}=\boxed{+\frac{|V_A|}{RC}}\ (\text{since }V_A\lt0)$$ $$\text{Phase 2 (}T_1\le t\le T_2\text{):}\quad \frac{dV_x}{dt}=-\frac{V_R}{RC}=\boxed{-\frac{V_R}{RC}}\ (\text{negative, since }V_R\gt0)$$
2. Part (a) — waveform. Starting from $V_x(0)=0$, $V_x$ ramps up linearly through phase 1, reaching $$V_x(T_1)=-\frac{V_A}{RC}\,T_1$$ then ramps back down linearly through phase 2 (slope $-V_R/RC$) until it crosses zero at $t=T_2$, at which instant the comparator ($(-)$ input crossing below the grounded $(+)$ input) switches $V_o$.
3. Part (c) — $T_2/T_1$. Setting $V_x(T_2)=0$: $$0=V_x(T_1)+\Big(-\frac{V_R}{RC}\Big)(T_2-T_1)=-\frac{V_A}{RC}T_1-\frac{V_R}{RC}(T_2-T_1)$$ $$-V_AT_1=V_R(T_2-T_1)\ \Rightarrow\ T_2-T_1=-\frac{V_AT_1}{V_R}\ \Rightarrow\ \boxed{\dfrac{T_2}{T_1}=1-\dfrac{V_A}{V_R}=1+\dfrac{|V_A|}{V_R}}$$ Notice $R$ and $C$ cancel completely — the ratio $T_2/T_1$ depends only on the unknown $V_A$ relative to the stable reference $V_R$, which is precisely why dual-slope conversion is insensitive to $R,C$ drift and tolerance.
4. Part (d) — limitations. (i) $V_A$ must stay essentially constant over the whole of $T_1$ (a true "sample," not a fast-varying signal) — the circuit needs a front-end sample-and-hold for anything but slowly-varying/DC inputs. (ii) Total conversion time $T_2$ varies with the input magnitude, so this is not a fixed-latency converter — unsuitable where deterministic timing matters. (iii) The integrator op-amp's output swing must accommodate $V_x(T_1)=|V_A|T_1/(RC)$ without saturating, bounding the usable $|V_A|$ for a given $T_1,R,C$. (iv) Comparator offset directly corrupts the zero-crossing detection of $T_2$, and integrator leakage/op-amp input bias current corrupts the ramp slopes — both need to be small relative to the smallest $V_A$ to be resolved. (v) $V_R$ must be an accurate, stable reference (any drift in $V_R$ maps directly into a scale error in the reported $V_A$). (vi) The switches ($\Phi_1,\Phi_2$ MOSFETs) must have low charge injection/leakage, or their clock feedthrough adds error at each transition. Overall, dual-slope is inherently slow (appropriate for a DVM-class application) rather than a fast general-purpose ADC.