Two RS flip-flops: logic equations, state table and state diagram: 22-Elec-A4 Digital Systems and Computers, December 2016, Q2

Question 2 (12 marks) — Two RS flip-flops: logic equations, state table and state diagram

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Check. The excitation network was redrawn from the printed figure. The two output OR gates feed $R_A$ and $S_A$; the four AND gates combine $X$, $\overline{X}$ and the flip-flop outputs, and the lower flip-flop's own $Q,\overline{Q}$ return to its $R_B,S_B$ inputs. The wiring that could be read unambiguously fixes $R_B=B,\,S_B=\overline{B}$ and the $X\!\oplus\!B$ toggle condition on $A$; a mirror reading (swap the roles of $X$ and $\overline{X}$) would merely exchange ‘up’ and ‘down’ in the count sequence. The solution commits to $X=0\Rightarrow$ up.

Given. Two clocked RS flip-flops $A$ (MSB) and $B$ (LSB); an inverter produces $\overline{X}$; four AND gates and two OR gates form the excitation logic. Find. the four drive equations, the full next-state table, and the state diagram.

Approach. Trace each flip-flop's $R,S$ from the gates, use the RS rule $Q^+ = S + \overline{R}\,Q$ (with $RS=0$) to fill an eight-row table over $(A,B,X)$, then read the two cyclic sequences.

[Figure not reproduced: Excitation network redrawn as a $T$-type realisation: $T_A = X\oplus B$ gates $R_A=A\,T_A$ and $S_A=\overline{A}\,T_A$; the lower flip-flop is wired as an unconditional toggle. See the official exam paper.]

Drive equations (part a). The lower flip-flop feeds its own outputs back: $\boxed{R_B=B,\quad S_B=\overline{B}}$, so it toggles every clock ($T_B=1$). The upper flip-flop is set/reset only when the toggle condition $T_A=X\oplus B=\overline{X}B+X\overline{B}$ is true, gated by the present $A$: $$\boxed{R_A=A\,(X\oplus B)=A\overline{X}B+AX\overline{B},\qquad S_A=\overline{A}\,(X\oplus B)=\overline{A}\,\overline{X}B+\overline{A}X\overline{B}}$$ By construction $R_A S_A = A\overline{A}(X\oplus B)=0$ and $R_B S_B = B\overline{B}=0$, so neither flip-flop is ever driven invalid.
Next-state rule. For RS, $Q^+=S+\overline{R}Q$. With the equations above this is the toggle law $A^+=A\oplus T_A=A\oplus(X\oplus B)$ and $B^+=\overline{B}$.
Fill the table (part b). Evaluate all eight $(A,B,X)$ rows.

A	B	X	$R_A S_A$	$R_B S_B$	$A^+ B^+$
0	0	0	0 0	0 1	0 1
0	0	1	0 1	0 1	1 1
0	1	0	0 1	1 0	1 0
0	1	1	0 0	1 0	0 0
1	0	0	0 0	0 1	1 1
1	0	1	1 0	0 1	0 1
1	1	0	1 0	1 0	0 0
1	1	1	0 0	1 0	1 0

Reading the sequences (part c). With $X=0$ the state $AB$ advances $00\to01\to10\to11\to00$ (binary up-count); with $X=1$ it runs $00\to11\to10\to01\to00$ (down-count). The machine is a 2-bit synchronous up/down counter with $X$ as the direction control; all four states are used, so it is trivially self-correcting.

State diagram. Solid direction $X=0$ counts up, $X=1$ counts down; each edge is one clock.

Item	Result
(a) $R_A,S_A$	$A(X\oplus B)$, $\overline{A}(X\oplus B)$
(a) $R_B,S_B$	$B$, $\overline{B}$ (toggle)
(b) Next state	$A^+=A\oplus X\oplus B$, $B^+=\overline{B}$
(c) Behaviour	2-bit up/down counter ($X=0$ up, $X=1$ down)

Topic. Analysis of a clocked RS sequential circuit; $T$-flip-flop realisation of a counter.

Key relations. RS characteristic equation $Q^+=S+\overline{R}Q$, constraint $RS=0$; toggle via $R=QT,\,S=\overline{Q}T$ giving $Q^+=Q\oplus T$.

Why this works. Splitting a toggle command $T$ into $R=QT$ (reset a 1) and $S=\overline{Q}T$ (set a 0) is the standard way to build a $T$ flip-flop from an RS cell and automatically satisfies $RS=0$. Because the LSB toggles every clock and the MSB toggles once per LSB cycle under $X\oplus B$, the pair realises a reversible binary counter.

Common pitfall. Applying the SR ‘forbidden’ row: here it can never occur, but students often tabulate $R=S=1$ anyway. Also, forgetting that $B$ appears in $A$'s excitation makes the up/down behaviour look like a mistake rather than the intended design.

Source. Mano & Ciletti §5.4-5.7 (analysis of clocked sequential circuits) and §6.4 (up/down counters); Wakerly §7.3, §8.4.

Question 2 of 6: Two RS flip-flops: logic equations, state table and state diagram

Question 2 (12 marks) — Two RS flip-flops: logic equations, state table and state diagram