Memory-mapped chip-select decoding: 22-Elec-A4 Digital Systems and Computers, December 2016, Q5

Question 5 (12 marks) — Memory-mapped chip-select decoding

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. RAM 4 KB at 0x8800; EPROM 2 KB at 0xB800; forbidden windows 0x9800–0x9FFF, 0xB600–0xB7FF, 0xC000–0xFFFF; a 74HC138 decoding $A_{15}A_{14}A_{13}$ into 8 KB pages $Y_0\ldots Y_7$. Find. bus widths and the active-low selects $E1,E2$.

Approach. Size each chip's internal address bus from its capacity, place its range in the decoder's 8 KB page, then add the minimum gating on $A_{12},A_{11}$ to carve the exact window and exclude the forbidden regions.

Address-decode block diagram. The 74HC138 selects 8 KB pages; $Y_4$ (0x8000-0x9FFF) gates the RAM and $Y_5$ (0xA000-0xBFFF) the EPROM, with $A_{12},A_{11}$ trimming each to its exact window.

Bus widths (part a). A 4 Kbyte RAM has $4096=2^{12}$ locations → 12 address lines $A_0\!-\!A_{11}$ and 8 data lines $D_0\!-\!D_7$. A 2 Kbyte EPROM has $2048=2^{11}$ → 11 address lines $A_0\!-\!A_{10}$ and 8 data lines. The 74HC138 takes 3 select lines $A_{13},A_{14},A_{15}$.
Locate the RAM range. RAM occupies $0\text{x}8800$ to $0\text{x}8800+0\text{x}0FFF=0\text{x}97FF$. Its top three address bits $A_{15}A_{14}A_{13}=100$ select $\boxed{Y_4}$ (the 8 KB page 0x8000-0x9FFF).
Trim the RAM window with $A_{12},A_{11}$. Inside $Y_4$ the four 2 KB sub-pages are 00:0x8000-0x87FF, 01:0x8800-0x8FFF, 10:0x9000-0x97FF, 11:0x9800-0x9FFF. The RAM needs the middle two ($A_{12}A_{11}=01$ or $10$), which is exactly $A_{12}\oplus A_{11}$; this also excludes the forbidden 0x9800-0x9FFF ($11$). With the active-low $Y_4$: $$\boxed{E1=Y_4+\overline{A_{12}\oplus A_{11}}=Y_4+(A_{12}\odot A_{11})}$$ i.e. $E1$ is low only when $Y_4=0$ and $A_{12}\ne A_{11}$.
Locate the EPROM range. EPROM occupies $0\text{x}B800$ to $0\text{x}BFFF$ (2 KB). Its top bits $A_{15}A_{14}A_{13}=101$ select $\boxed{Y_5}$ (page 0xA000-0xBFFF).
Trim the EPROM window. 0xB800-0xBFFF is the top sub-page $A_{12}A_{11}=11$, which excludes the forbidden 0xB600-0xB7FF ($A_{12}A_{11}=10$). Hence $$\boxed{E2=Y_5+\overline{A_{12}\cdot A_{11}}=Y_5+(\overline{A_{12}}+\overline{A_{11}})}$$ low only when $Y_5=0$ and both $A_{12}=A_{11}=1$.

Item	Result
RAM bus	12 address ($A_0$-$A_{11}$), 8 data
EPROM bus	11 address ($A_0$-$A_{10}$), 8 data
RAM page / EPROM page	$Y_4$ / $Y_5$
$E1$ (RAM, active low)	$Y_4+(A_{12}\odot A_{11})$
$E2$ (EPROM, active low)	$Y_5+\overline{A_{12}A_{11}}$

Topic. Partial address decoding and chip-select generation with a 3:8 decoder.

Key relations. A device of $2^n$ bytes uses $n$ internal address lines; the remaining high lines decode the base. A 74HC138 output is active-low, so a chip select is $E=\overline{Y_k}\cdot(\text{window})$ expressed as $E=Y_k+\overline{\text{window}}$.

Why this works. The decoder resolves 8 KB pages with three lines; because both chips sit at non-8 KB-aligned bases, a little $A_{12}/A_{11}$ logic carves the exact window while simultaneously fencing off the reserved regions — no wide comparator needed.

Common pitfall. Assuming the 4 KB RAM is 4 KB-aligned: 0x8800 straddles two 2 KB sub-pages, so a single $A_{12}$ term is wrong — the correct gate is $A_{12}\oplus A_{11}$. Forgetting the decoder outputs are active-low inverts the whole expression.

Source. Hamacher et al. §8.2 (memory system organization) and §3.x (I/O and address decoding); Mano & Ciletti §7.2 (decoders).

Question 5 of 6: Memory-mapped chip-select decoding

Question 5 (12 marks) — Memory-mapped chip-select decoding