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22-Elec-A4 Digital Systems and Computers · December 2016

Question 4 of 6: NOR universality, combinational vs sequential, synchronous vs asynchronous counters

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, December 2016 — 07-Elec-A4 Digital Systems & Computers. Three hours, closed book, one approved Casio or Sharp calculator. Six questions are printed and any five constitute a complete exam; every question is worth 12 points with the per-part breakdown printed on page 1. A flip-flop excitation table and a sheet of Boolean identities are attached as page 6. All six questions are solved below so the set works as a complete study resource.

Reference texts.

Question 4 (12 marks) — NOR universality, combinational vs sequential, synchronous vs asynchronous counters

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Part (a) — NOR is universal. Using $\overline{A+A}=\overline{A}$, De Morgan gives every basic gate from NOR gates alone:

NOT: Y = (A+A)' = A'AA'OR: Y = ((A+B)')' = A+BABA+BAND: Y = (A'+B')' = A . BABA'B'A . B
NOR-only realisations of NOT, OR and AND. Bubbled OR symbols are NOR gates; each construction follows directly from De Morgan.

Part (b) — combinational vs sequential. A combinational circuit is memoryless: its outputs are a pure Boolean function of the present inputs, so a change propagates to the output after only the gate delays. A sequential circuit adds storage elements (latches or flip-flops) and feedback, so its output depends on the present inputs and the stored state (the history). In a synchronous sequential circuit the state can change only at an active clock edge, so an input change is not reflected until the clock ticks; the same input can produce different outputs depending on the state the machine is in. That state-dependence and clock-gating is the defining difference.

Part (c) — synchronous vs asynchronous counter. Both count, but they differ in how the clock reaches each stage.

Synchronous: one common clockAsynchronous (ripple)TQ0TQ1TQ2Clkall flip-flops toggle on the SAME edgeTQ01TQ11TQ21Clkeach Q clocks the next stage (delays add up)
Left: synchronous counter — every flip-flop shares the same clock and toggles on the same edge (state logic sets each $T$). Right: asynchronous (ripple) counter — each stage's output clocks the next, so edges ripple through and delays accumulate.

In the synchronous counter a single clock line drives every flip-flop, so all stages that must change do so simultaneously on one edge; the per-stage toggle enables come from combinational state logic. Total settling time is one flip-flop delay plus the logic, independent of width. In the asynchronous (ripple) counter only the first flip-flop sees the external clock; each subsequent flip-flop is clocked by the previous stage's output. The counting edge therefore ripples down the chain and the worst-case delay is $n$ flip-flop delays, which produces transient (glitch) states and limits speed. That shared-clock versus chained-clock distinction is exactly why one is synchronous and the other is not.