22-Elec-A4 Digital Systems and Computers · May 2016

Question 2 of 6: Analysis of a two JK flip-flop sequential circuit

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2016 — 07-Elec-A4 Digital Systems & Computers. Three hours, closed book, one approved Casio or Sharp calculator. Six questions, each worth 12 points; five questions constitute a complete exam. A flip-flop excitation table and a list of Boolean identities are printed on the last page. Every one of the six questions is solved below, because the set is intended as a study resource rather than an exam script.

Reference texts. M. Morris Mano & M. D. Ciletti, Digital Design (6th ed.), ch. 3 (map simplification, prime implicants, hazards), ch. 5–6 (sequential logic, counters); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.), §3.7 (three-state outputs), §4.4 (timing hazards and consensus terms), ch. 8 (counters); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.), ch. 1–2 (processor structure, registers), ch. 3 (memory-mapped I/O).

Check: segment-to-pin assignment in Question 6. Figure 6.1 shows the buffer chip driving the eight segment lines a…h from Port B pins PB7–PB0, but does not print which pin drives which segment. Throughout Question 6 the conventional weighting a = PB0, b = PB1, …, g = PB6, h = PB7 (decimal point) is assumed and stated explicitly, exactly as the paper's own rubric invites ("the candidate is urged to submit…a clear statement of any assumptions made"). Every bit pattern below is derived from that one assumption; a different pin order permutes the bits but changes no part of the method.

Question 2: Analysis of a two JK flip-flop sequential circuit (12 points)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A synchronous circuit built from two JK flip-flops A and B sharing one clock CK, with a single external input X. Both clock inputs carry an inversion bubble, so the machine is negative-edge triggered. Reading the schematic on page 2 of the paper: X and the B output feed an exclusive-OR gate whose output drives J_A; the B rail also runs directly to K_A; X passes through an inverter to form X′, which meets the A rail at an AND gate driving J_B, and meets the A′ rail at an OR gate driving K_B.

Given data
Item	Value
State variables	A (flip-flop A), B (flip-flop B)
External input	X (one bit)
Flip-flop type	JK, negative-edge triggered (bubbled clock inputs)
Gates present	one XOR, one AND, one OR, one inverter
Characteristic equation	$Q^{+} = JQ' + K'Q$

Find. The four excitation expressions in terms of X, A and B; the eight-row state transition table giving A⁺B⁺ for every combination of present state and input; and the corresponding state transition diagram.

[Figure not reproduced: Fig Q2.1 — The circuit of page 2 redrawn from the printed figure. Signal names A, A′, B, B′ are the flip-flop outputs fed back to the gate inputs; crossings without a solid junction dot are not connections. Both clock inputs are bubbled, so the machine responds to the falling edge of CK. See the official exam paper.]

Approach. Read the four excitation expressions straight off the gates, substitute them into the JK characteristic equation $Q^{+} = JQ' + K'Q$ for each flip-flop, and evaluate over all eight combinations of (X, A, B). The resulting next-state column is the transition table, and drawing one arc per row gives the diagram.

Part (a): read the excitation expressions off the schematic. Tracing each gate back to its sources: $$J_A = X \oplus B \qquad K_A = B$$ $$J_B = A\,X' \qquad K_B = X' + A'$$ Two of these deserve a comment. K_A is taken directly from the B output with no gate at all, which is why the drawing appears to have fewer gates than the four expressions suggest. And K_B is an OR of two complemented signals, so by De Morgan it can equally be written $K_B = (XA)'$ — it is 0 only when X and A are both 1. $$\boxed{J_A = X \oplus B,\quad K_A = B,\quad J_B = A X',\quad K_B = X' + A'}$$
Recall the JK characteristic equation. The excitation table printed on the last page of the paper (Q, Q⁺, J, K rows) is the inverse mapping; for analysis the forward form is more convenient: $$Q^{+} = J\,Q' + K'\,Q$$ which reproduces the four familiar behaviours — hold for JK = 00, reset for 01, set for 10, and toggle for 11.
Part (b): evaluate the excitation inputs for all eight rows. With X, A, B running through their eight combinations, and remembering that X′ is 1 exactly when X is 0:
Excitation inputs
X A B J_A = X ⊕ B K_A = B J_B = AX′ K_B = X′ + A′

0 0 0 0 0 0 1

0 0 1 1 1 0 1

0 1 0 0 0 1 1

0 1 1 1 1 1 1

1 0 0 1 0 0 1

1 0 1 0 1 0 1

1 1 0 1 0 0 0

1 1 1 0 1 0 0

Note that K_B is 0 only in the last two rows, where X = A = 1, and that J_B is 1 only when A = 1 with X = 0 — so J_B and K_B are never both 1 and flip-flop B never toggles.

Excitation inputs
X	A	B	J_A = X ⊕ B	K_A = B	J_B = AX′	K_B = X′ + A′
0	0	0	0	0	0	1
0	0	1	1	1	0	1
0	1	0	0	0	1	1
0	1	1	1	1	1	1
1	0	0	1	0	0	1
1	0	1	0	1	0	1
1	1	0	1	0	0	0
1	1	1	0	1	0	0

Apply the characteristic equation to obtain the next state. Substituting each row into $A^{+} = J_A A' + K_A' A$ and $B^{+} = J_B B' + K_B' B$ gives the state transition table asked for:

State transition table
X	Present A B	J_A K_A	J_B K_B	Next A⁺ B⁺	Action
0	0 0	0 0	0 1	0 0	A holds, B resets
0	0 1	1 1	0 1	1 0	A toggles, B resets
0	1 0	0 0	1 1	1 1	A holds, B toggles
0	1 1	1 1	1 1	0 0	A toggles, B toggles
1	0 0	1 0	0 1	1 0	A sets, B resets
1	0 1	0 1	0 1	0 0	A resets, B resets
1	1 0	1 0	0 0	1 0	A sets, B holds
1	1 1	0 1	0 0	0 1	A resets, B holds

$$\boxed{\text{See the eight next-state entries above; every one of the four states is reachable.}}$$ Two rows are worth checking by hand as a guard against transcription slips. In row 3 (X = 0, AB = 10) the inputs are J_AK_A = 00 so A holds at 1, and J_BK_B = 11 so B toggles from 0 to 1, giving 11. In row 8 (X = 1, AB = 11) the inputs are 01 and 00, so A is reset to 0 while B holds at 1, giving 01.

Part (c): draw the state transition diagram. Each of the eight table rows becomes one directed arc labelled with the value of X that causes it. Since the outputs are simply the state variables A and B, this is a Moore machine and no output label is needed on the arcs. $$\boxed{\begin{aligned} X=0:&\quad 00 \to 00,\; 01 \to 10,\; 10 \to 11,\; 11 \to 00\\ X=1:&\quad 00 \to 10,\; 01 \to 00,\; 10 \to 10,\; 11 \to 01 \end{aligned}}$$

Fig Q2.2 — State transition diagram; each circle is labelled with the state AB and each arc with the input value that drives it. State 00 holds itself when X = 0 and state 10 holds itself when X = 1.

The behaviour is easy to describe in words once the diagram is drawn. Holding X at 0 sends the machine round the four-state cycle 00 → 00 from rest, but starting anywhere else it walks 01 → 10 → 11 → 00 and then parks in 00; holding X at 1 drives it toward 10 and holds it there. There are no unreachable or locked-out states, and no state has an undefined successor, so the machine is well formed for both input values.

Question 2 — final results
Quantity	Result
(a) J_A	X ⊕ B
(a) K_A	B
(a) J_B	A·X′
(a) K_B	X′ + A′ = (XA)′
(b) next state, X = 0	00→00, 01→10, 10→11, 11→00
(b) next state, X = 1	00→10, 01→00, 10→10, 11→01
(c) self-loops	state 00 for X = 0; state 10 for X = 1
Machine type / triggering	Moore, negative-edge triggered; all four states reachable

Topic. Analysis of a clocked sequential circuit built from JK flip-flops.

Key relations. JK characteristic equation $Q^{+} = J Q' + K' Q$; the four JK modes (00 hold, 01 reset, 10 set, 11 toggle); De Morgan's theorem $X' + A' = (XA)'$, used to recognise the OR-of-complements gate as a NAND.

Why this works. Analysis is the reverse of design. In design one starts from a desired sequence and uses the excitation table (Q, Q⁺ → J, K) to work backwards to gate equations; in analysis the gates are given, so the forward characteristic equation is the right tool. Because the two flip-flops share one clock edge, both next-state values are computed from the same present state — the new A must never be used when computing the new B. That simultaneity is what distinguishes a synchronous machine from the ripple counter of Question 3, and it is why the whole analysis reduces to filling in a table rather than reasoning about propagation order.

Common pitfall. The classic error is a “cascade” evaluation in which the freshly computed A⁺ is substituted into J_B; that models a ripple circuit, not this one, and gives wrong entries in the rows where A changes. A second trap on this particular schematic is misreading K_A: because it is fed by a bare wire from the B output rather than by a gate, candidates often assume a gate must be hidden somewhere and invent one. Trace every input pin back to a source before writing any expression, and confirm that each rail in the drawing has at least one consumer.

Source. Mano & Ciletti, Digital Design 6th ed., §5.4–5.7 (analysis of clocked sequential circuits, state tables and state diagrams, flip-flop characteristic and excitation tables); Wakerly, Digital Design 5th ed., §7.4.

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