22-Elec-A4 Digital Systems and Computers · May 2016

Question 4 of 6: A static memory cell built from cascaded inverters and tri-state buffers

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, May 2016 — 07-Elec-A4 Digital Systems & Computers. Three hours, closed book, one approved Casio or Sharp calculator. Six questions, each worth 12 points; five questions constitute a complete exam. A flip-flop excitation table and a list of Boolean identities are printed on the last page. Every one of the six questions is solved below, because the set is intended as a study resource rather than an exam script.

Reference texts. M. Morris Mano & M. D. Ciletti, Digital Design (6th ed.), ch. 3 (map simplification, prime implicants, hazards), ch. 5–6 (sequential logic, counters); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.), §3.7 (three-state outputs), §4.4 (timing hazards and consensus terms), ch. 8 (counters); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.), ch. 1–2 (processor structure, registers), ch. 3 (memory-mapped I/O).

Check: segment-to-pin assignment in Question 6. Figure 6.1 shows the buffer chip driving the eight segment lines a…h from Port B pins PB7–PB0, but does not print which pin drives which segment. Throughout Question 6 the conventional weighting a = PB0, b = PB1, …, g = PB6, h = PB7 (decimal point) is assumed and stated explicitly, exactly as the paper's own rubric invites ("the candidate is urged to submit…a clear statement of any assumptions made"). Every bit pattern below is derived from that one assumption; a different pin order permutes the bits but changes no part of the method.

Question 4: A static memory cell built from cascaded inverters and tri-state buffers (12 points)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The design starts from a one-bit static storage cell drawn on page 3 of the paper. Two inverters are connected in cascade, so the node at the far end of the pair carries the same logic value as the cell node A. Two tri-state buffers close the picture: T₁ passes the data input D forward to the cell node, and T₂ passes the far-end value back to the same node, completing a storage loop.

Given data
Item	Value
Storage element	two cascaded inverters (net gain +1 around the loop)
T₁	tri-state buffer from D to the cell node; enable shown with an inversion bubble
T₂	tri-state buffer from the far end of the inverter pair back to the cell node; enable shown without a bubble
Control	W̅ — one bit, driving both enables directly
Cell node	A, also the cell's output

Find. Whether W̅ is active-low or active-high, with the hold and update mechanisms described; the eight-row truth table of T₁ and T₂ in terms of A, D and W̅; and the minimum duration for which W̅ must be asserted.

[Figure not reproduced: Fig Q4.1 — The memory cell redrawn from the printed figure. T 1 's enable carries an inversion bubble and T 2 's does not, so the two buffers are driven in opposition by the single control line and can never conduct simultaneously. See the official exam paper.]

Approach. The enable polarity of the two buffers is the whole question: identify which buffer conducts for each value of W̅, then describe the resulting write path and hold path, tabulate the buffer outputs (using Z for the high-impedance state), and finally count the gate delays around the storage loop to obtain the minimum pulse width.

Part (a): determine the polarity from the enable bubbles. The control line runs to both buffers, but T₁'s enable input carries an inversion bubble while T₂'s does not. A bubbled enable conducts when its control is low; a plain enable conducts when its control is high. Therefore $$\overline{W} = 0 \;\Rightarrow\; T_1 \text{ conducting},\ T_2 \text{ high-impedance}$$ $$\overline{W} = 1 \;\Rightarrow\; T_1 \text{ high-impedance},\ T_2 \text{ conducting}$$ Since the cell is written — that is, the write function is performed — when the control line is low, and the overbar on the name says as much, $$\boxed{\overline{W} \text{ is ACTIVE-LOW}}$$
Describe (i) how the value is held. With W̅ held at 1, T₁ is off, so the data input D is completely disconnected from the cell and cannot disturb it. T₂ is on, so the output of the second inverter is fed back onto the cell node A. The two inverters in cascade give a net non-inverting gain around the loop, so whatever value A holds is regenerated onto A continuously. This is positive feedback with a loop gain greater than unity at the two stable points, so the cell latches at either A = 0 or A = 1 and actively restores itself against leakage and noise — the defining property of a static memory cell, and the reason it needs no refresh.
Describe (ii) how the value is updated. Driving W̅ low turns T₁ on and T₂ off. Breaking the feedback path is essential: if both buffers conducted at once and D disagreed with the stored value, the driver in T₁ and the driver in T₂ would fight for the same node, producing an indeterminate level and a large crowbar current. With T₂ off, the cell node is driven solely by D through T₁. The new value propagates through the first inverter to A′ and through the second back to the buffer input, so that by the time W̅ is released the feedback loop is already presenting the new value and the cell latches it. The complementary bubbling is thus not a cosmetic detail but the mechanism that makes the cell work at all.

Part (b): tabulate the tri-state outputs. Writing Z for the high-impedance state, and remembering that T₂'s input is the far end of the inverter pair and therefore carries the value A itself:

Truth table for the two tri-state buffer outputs
A	D	W̅	T₁	T₂	Cell node after the operation
0	0	0	0	Z	0 (written from D)
0	1	0	1	Z	1 (written from D)
1	0	0	0	Z	0 (written from D)
1	1	0	1	Z	1 (written from D)
0	0	1	Z	0	0 (held)
0	1	1	Z	0	0 (held; D ignored)
1	0	1	Z	1	1 (held; D ignored)
1	1	1	Z	1	1 (held)

$$\boxed{T_1 = D \text{ when } \overline{W}=0,\ \text{else } Z; \qquad T_2 = A \text{ when } \overline{W}=1,\ \text{else } Z}$$ Two features of the table are worth pointing out. Exactly one of T₁ and T₂ is ever driving — the Z entries are in complementary columns on every row — and in the four hold rows the value of D has no effect whatever on the outputs, which is the tabular statement of “the input is isolated”.

Part (c): minimum duration of the write pulse. A write is successful only if the new value has travelled all the way round the storage loop before the feedback path is restored; otherwise, when T₂ switches back on it will still be presenting the old value and will fight or overwrite the new one. The new value must therefore propagate through T₁, then through the first inverter to A′, then through the second inverter to the input of T₂: $$t_{\overline{W}(\min)} = t_{T_1} + 2\,t_{\text{inv}} + t_{\text{setup}}$$ $$\boxed{\overline{W} \text{ must stay low for at least the buffer delay plus TWO inverter delays}}$$ In the simplified terms the question invites, the answer is that W̅ must be active for at least the round-trip delay of the two cascaded inverters — long enough for the cell to have regenerated the new value itself. A safe design adds margin for the enable turn-off time of T₂ and for the worst-case slow process corner, and the data input D must additionally be stable for the whole of that interval (a setup requirement) and briefly afterwards (a hold requirement), exactly as for a conventional latch. If W̅ is released too early, the outcome is not merely a lost write but a metastable cell, since the loop may be released with the two inverters in disagreement.

Question 4 — final results
Quantity	Result
(a) polarity of W̅	Active-low
(a)(i) hold	W̅ = 1: T₁ off, T₂ on — feedback loop closed, D isolated, value regenerated
(a)(ii) update	W̅ = 0: T₁ on, T₂ off — loop broken, cell node driven by D
(b) T₁	D when W̅ = 0; high impedance (Z) when W̅ = 1
(b) T₂	A when W̅ = 1; high impedance (Z) when W̅ = 0
(b) contention	never — the two enables are complementary on all eight rows
(c) minimum pulse width	t_T1 + 2 t_inv (+ margin): the value must circulate the whole loop before T₂ re-enables

Topic. The static latch: cross-coupled inverters, three-state buffers, and write-pulse timing.

Key relations. A three-state buffer has three output states — 0, 1 and Z (high impedance) — selected by an enable that may be active-high or active-low as marked by an inversion bubble. Two inverters in cascade give unity (non-inverting) gain, so a closed loop of two inverters has two stable states. Minimum write width $t_{\overline{W}} \ge t_{\text{buf}} + 2\,t_{\text{inv}}$.

Why this works. Storage in a static cell is bistability, not charge. The loop formed by the two inverters has three mathematical solutions — A = 0, A = 1, and an unstable midpoint — and any drift away from the midpoint is amplified by the loop gain until the cell saturates at one rail. Writing therefore cannot simply be a matter of forcing the node; the existing feedback must be removed first, or the write driver would be competing with an active restoring loop. That is why one control line drives two enables of opposite polarity: it guarantees, structurally rather than by timing, that the loop is open exactly when the driver is on. This same cell, with the buffers replaced by pass transistors and a second bit line added, is the six-transistor SRAM cell used throughout modern cache memory.

Common pitfall. The most common error in part (b) is entering 0 or 1 in a column where the buffer is disabled. A disabled three-state output is not low — it is disconnected, and writing 0 there implies a drive fight that the circuit is specifically designed to avoid. A second error in part (c) is answering “one gate delay” or “until D is stable”; the requirement is set by the loop, so both inverters must be counted, and it is the closing of the feedback path rather than the arrival of D that defines success.

Source. Wakerly, Digital Design 5th ed., §3.7.3 (three-state outputs and bus contention) and §7.2 (latches, the S-R and D latch); Hamacher et al., Computer Organization and Embedded Systems 6th ed., §8.2 (static RAM cell structure and timing).

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