22-Elec-A4 Digital Systems and Computers · May 2016
Question 6 of 6: Driving six multiplexed seven-segment displays
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, May 2016 — 07-Elec-A4 Digital Systems & Computers. Three hours, closed book, one approved Casio or Sharp calculator. Six questions, each worth 12 points; five questions constitute a complete exam. A flip-flop excitation table and a list of Boolean identities are printed on the last page. Every one of the six questions is solved below, because the set is intended as a study resource rather than an exam script.
Reference texts. M. Morris Mano & M. D. Ciletti, Digital Design (6th ed.), ch. 3 (map simplification, prime implicants, hazards), ch. 5–6 (sequential logic, counters); J. F. Wakerly, Digital Design: Principles and Practices (5th ed.), §3.7 (three-state outputs), §4.4 (timing hazards and consensus terms), ch. 8 (counters); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.), ch. 1–2 (processor structure, registers), ch. 3 (memory-mapped I/O).
Check: segment-to-pin assignment in Question 6. Figure 6.1 shows the buffer chip driving the eight segment lines a…h from Port B pins PB7–PB0, but does not print which pin drives which segment. Throughout Question 6 the conventional weighting a = PB0, b = PB1, …, g = PB6, h = PB7 (decimal point) is assumed and stated explicitly, exactly as the paper's own rubric invites ("the candidate is urged to submit…a clear statement of any assumptions made"). Every bit pattern below is derived from that one assumption; a different pin order permutes the bits but changes no part of the method.
Question 6: Driving six multiplexed seven-segment displays (12 points)
Given. The design starts from a memory-mapped display subsystem: one shared eight-bit segment bus drives all six digits, and a second port selects which digit's common cathode is grounded.
Given data
Item
Value
Displays
six common-cathode seven-segment units, numbered #5 (leftmost) to #0 (rightmost)
Segment drive
Port B, PB7–PB0, through a buffer chip; the bus is common to all six displays
Digit selection
Port D, PD5–PD0, each driving a transistor that grounds one common cathode
Port B address
$1004, i.e. $\mathtt{1004}_{16}$
Port D address
$1008, i.e. $\mathtt{1008}_{16}$
Segment weighting (assumed)
PB0 = a, PB1 = b, PB2 = c, PB3 = d, PB4 = e, PB5 = f, PB6 = g, PB7 = h (point)
Instructions available
ldaa (load accumulator A), staa (store accumulator A)
Find. An assembly sequence that lights the digit 6 on display #0, and an algorithm — with its Port B bit patterns — that makes all six displays appear to show 09.05.16 at once.
[Figure not reproduced: Fig Q6.1 — The display subsystem redrawn from Figure 6.1 of the paper. Because one segment bus feeds every display in parallel, the pattern written to Port B appears on all six units at the same instant; only the display whose cathode Port D has grounded actually lights. See the official exam paper.]
Approach. Because a common-cathode display lights a segment when its anode is high and its cathode is grounded, the Port B pattern selects which segments and the Port D pattern selects which digit. Part (a) is therefore two writes; part (b) exploits persistence of vision by cycling those two writes through all six digits faster than the eye can follow.
Establish the segment pattern for the digit 6. On a seven-segment display the numeral 6 lights segments a, c, d, e, f and g — segment b (the upper-right stroke) is dark, which is what distinguishes a 6 from an 8, and the decimal point h is dark. With the stated weighting, bit n is 1 when the corresponding segment is lit:
$$\text{PB7..PB0} = 0\,1\,1\,1\,1\,1\,0\,1$$
$$\boxed{\text{Port B} = \mathtt{7D}_{16} \text{ for the digit } 6}$$
A common-cathode display needs a logic 1 to light a segment, since current flows from the driven anode through the LED to the grounded cathode. For a common-anode part every bit would be inverted, giving $\mathtt{82}_{16}$ instead — a distinction always worth stating explicitly.
Establish the digit-enable pattern for display #0. Each Port D bit drives one transistor that pulls the corresponding display's common cathode to ground, and the displays are numbered so that PDn serves display #n. To light display #0 alone, PD0 is set and every other bit cleared:
$$\boxed{\text{Port D} = \mathtt{01}_{16}}$$
Enabling more than one bit here would ground more than one cathode, and since all six anodes see the same segment pattern, every enabled digit would show the same numeral — which is exactly the problem part (b) sets out to solve.
Part (a): write the instruction sequence. Two loads and two stores are all that is required, and the order matters slightly: writing the segment pattern before enabling the digit avoids briefly displaying whatever pattern was previously left in Port B.
ldaa #$7D ; segment pattern for the digit '6'
staa $1004 ; -> Port B, drives segments a,c,d,e,f,g on ALL displays
ldaa #$01 ; digit-select mask: PD0 only
staa $1008 ; -> Port D, grounds the cathode of display #0
The immediate-addressing ‘#’ prefix on the loads is essential: ldaa $7D without it would load the contents of memory location $\mathtt{007D}_{16}$ rather than the constant. With these four instructions display #0 shows a steady 6 and the other five displays remain dark, since their cathodes are floating.
Part (b): recognise why six digits cannot be displayed statically. The single shared segment bus makes simultaneous static display impossible: Port B holds one pattern at a time, so any two digits enabled together necessarily show the same numeral. The standard solution is time-division multiplexing — illuminate the six digits one at a time in rapid rotation, so that each is lit for one sixth of the cycle and the eye, whose flicker-fusion threshold is around 50–60 Hz, integrates the sequence into six steady digits.
Derive the six Port B patterns for 09.05.16. The string maps onto the displays from left to right, so #5 shows 0, #4 shows 9 with its decimal point, #3 shows 0, #2 shows 5 with its decimal point, #1 shows 1, and #0 shows 6. Setting the decimal point simply means also setting PB7, that is adding $\mathtt{80}_{16}$:
Port B and Port D patterns for the six frames
Display
Digit
Segments lit
PB7..PB0
Port B
Port D
#5
0
a b c d e f
0011 1111
3F16
2016
#4
9 .
a b c d f g + point
1110 1111
EF16
1016
#3
0
a b c d e f
0011 1111
3F16
0816
#2
5 .
a c d f g + point
1110 1101
ED16
0416
#1
1
b c
0000 0110
0616
0216
#0
6
a c d e f g
0111 1101
7D16
0116
The six Port D masks are single, distinct bits that between them tile PD5–PD0, summing to $\mathtt{3F}_{16}$ — a useful check that no digit has been omitted or enabled twice.
State the algorithmic sequence. The refresh loop runs forever in the background, typically from a timer interrupt so that the main program is free to compute:
Store the six segment patterns 3F, EF, 3F, ED, 06, 7D (hexadecimal) in a table in memory, indexed by display number 5 down to 0.
Write $\mathtt{00}_{16}$ to Port D, blanking all digits.
Fetch the segment pattern for the next display in the rotation and write it to Port B.
Write that display's single-bit enable mask to Port D, lighting only that digit.
Wait for one time slot — see the timing calculation below.
Advance the index to the next display, wrapping from #0 back to #5, and repeat from step 2 indefinitely.
$$\boxed{\text{blank} \to \text{write segments} \to \text{enable one digit} \to \text{wait} \to \text{next digit, repeat}}$$
Step 2 is the one candidates most often omit, yet it is what prevents ghosting. If the digit currently enabled is left on while the next segment pattern is written, that digit displays the wrong numeral for the write-to-write interval, and the result is a faint shadow of each digit on its neighbour. Blanking Port D first guarantees that no display is ever enabled while the segment bus is changing.
Size the refresh rate. The complete rotation must repeat above the flicker-fusion frequency. Designing for a comfortable 100 Hz refresh of the whole display:
$$t_{\text{slot}} = \frac{1}{f_{\text{refresh}} \times N_{\text{digits}}} = \frac{1}{100 \times 6} = 1.667\ \text{ms}$$
$$\boxed{t_{\text{slot}} \approx 1.67\ \text{ms per digit at a 100 Hz refresh}}$$
At the 60 Hz minimum the slot would be 2.78 ms, so anything from roughly one to three milliseconds per digit is acceptable. Two consequences follow. Each LED is on for only one sixth of the time, so its average brightness is one sixth of the static case — multiplexed displays are therefore run at a correspondingly higher peak current, which the 100 Ω series resistors and the buffer chip must be rated for. And only one digit's worth of segment current flows at any instant, so the buffer chip and the supply see a fraction of the current that six statically-driven displays would demand: that reduction, together with the saving of forty-two individual drive lines down to fourteen, is the real reason multiplexing is used.
Fig Q6.2 — Segment naming (Fig 6.2 of the paper) with the segments for the numeral 6 highlighted, and the assumed bit weighting that turns those segments into the Port B byte 7D16.
Question 6 — final results
Quantity
Result
(a) Port B pattern for ‘6’
0111 1101 = 7D16 (segments a, c, d, e, f, g lit)
(a) Port D pattern for display #0
0000 0001 = 0116
(a) instruction sequence
ldaa #7D → staa 1004; ldaa #01 → staa 1008 (all hexadecimal)
(b) technique
Time-division multiplexing (scanned display) using persistence of vision
(b) Port B patterns, #5…#0
3F, EF, 3F, ED, 06, 7D (hexadecimal)
(b) Port D patterns, #5…#0
20, 10, 08, 04, 02, 01 (hexadecimal); they sum to 3F16
(b) refresh timing
1.67 ms per digit for a 100 Hz refresh (2.78 ms at the 60 Hz limit)
(b) essential ordering detail
Blank Port D before changing Port B, to prevent ghosting