22-Elec-A4 Digital Systems and Computers · May 2016

Question 3 of 6: Asynchronous binary and decade counters using T flip-flops

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Question 3: Asynchronous binary and decade counters using T flip-flops (12 points)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The design starts from a required counting sequence and a fixed flip-flop type. Part (a)–(b) ask for the full four-bit binary sequence, and parts (c)–(d) for the truncated ten-state sequence, both realised asynchronously (as a ripple counter) from T flip-flops.

Find. The state transition tables for both sequences, and ripple-counter schematics realising each from T flip-flops, with the decade version derived from the binary one.

Approach. In a ripple counter, bit 0 toggles on every clock and each higher bit toggles once per fall of the bit below it, so the T inputs are all tied to logic 1 and the design work lies entirely in the clock routing. Modulus truncation is then achieved by decoding the first unwanted state and feeding that decode back to the asynchronous clear inputs.

1. Part (a): the state transition table for the modulus-16 counter. An up-counter simply adds one each clock, so the table is the natural binary count with wrap-around:

   Four-bit asynchronous up-counter

   Clock	Q3Q2Q1Q0	Next	Clock	Q3Q2Q1Q0	Next
   0	0000	0001	8	1000	1001
   1	0001	0010	9	1001	1010
   2	0010	0011	10	1010	1011
   3	0011	0100	11	1011	1100
   4	0100	0101	12	1100	1101
   5	0101	0110	13	1101	1110
   6	0110	0111	14	1110	1111
   7	0111	1000	15	1111	0000

   All sixteen states appear exactly once before the sequence repeats, so the counter is of full modulus and $\log_2 16 = 4$ flip-flops are both necessary and sufficient.
2. Extract the toggle pattern. Reading down each column of the table reveals the property that makes a ripple counter possible: $Q_0$ changes on every count; $Q_1$ changes only when $Q_0$ goes from 1 to 0; $Q_2$ only when $Q_1$ goes from 1 to 0; $Q_3$ only when $Q_2$ does. In general $$Q_{n}\ \text{toggles} \iff Q_{n-1}\ \text{falls from } 1 \text{ to } 0$$ Since the required behaviour of every stage is “toggle whenever you are clocked”, and the T flip-flop's characteristic equation is $Q^{+} = T \oplus Q$, setting $T = 1$ gives $Q^{+} = Q'$ — exactly what is wanted: $$\boxed{T_0 = T_1 = T_2 = T_3 = 1}$$
3. Part (b): build the ripple counter. With every T input tied high, the only remaining design decision is where each stage gets its clock. Using negative-edge-triggered flip-flops (clock inputs bubbled), stage n is clocked from $Q_{n-1}$, because that output's falling edge is precisely the event that must toggle stage n. The external clock drives stage 0 only. $$\boxed{\text{CK} \to \text{FF}_0;\quad Q_0 \to \text{CK}_1;\quad Q_1 \to \text{CK}_2;\quad Q_2 \to \text{CK}_3;\quad \text{all } T = 1}$$ Had positive-edge-triggered flip-flops been chosen instead, the same counter is obtained by clocking each stage from $Q'_{n-1}$ rather than $Q_{n-1}$ — the complement rises exactly when the true output falls. Either answer is correct provided the edge sense and the tapped output are stated consistently.

4. Part (c): the state transition table for the decade counter. A decade counter uses ten of the sixteen states, counting 0000 through 1001 and then returning to zero. The six states 1010 through 1111 are unused:

   Decade (modulus-10) counter

   Count	Q3Q2Q1Q0	Next state
   0	0000	0001
   1	0001	0010
   2	0010	0011
   3	0011	0100
   4	0100	0101
   5	0101	0110
   6	0110	0111
   7	0111	1000
   8	1000	1001
   9	1001	0000

   Ten states still require four flip-flops, since $2^3 = 8 < 10 \le 16 = 2^4$; the counter is therefore a truncated four-bit counter rather than a smaller one.
5. Part (d): truncate the ripple counter with an asynchronous clear. Following the hint, take the counter of part (b) unchanged and add a decoder that detects the first unwanted state and immediately clears every stage. After the count 1001 the ripple counter naturally advances to 1010, so 1010 is the state to decode. Only two bits need to be examined, because 1010 is the first count at which $Q_3$ and $Q_1$ are simultaneously 1 — below it, $Q_3$ is 1 only in 1000 and 1001, where $Q_1$ is 0. Hence $$\overline{\text{CLR}} = \overline{Q_3 \cdot Q_1}$$ so a two-input NAND driving the active-low asynchronous clear of all four flip-flops is sufficient: $$\boxed{\text{decade counter} = \text{part (b) counter} + \text{NAND}(Q_3, Q_1) \to \overline{\text{CLR}}\ \text{of all four stages}}$$ Decoding all four bits of 1010 as $Q_3 Q_2' Q_1 Q_0'$ would also work, but the two-input NAND is the minimal decode and is what a 7490-style device does internally.
6. Explain what actually happens at the truncation. The state 1010 does appear, but only for the propagation delay of the NAND plus the clear path — typically a few nanoseconds — after which the counter is forced to 0000. That transient glitch is inherent to the asynchronous-clear technique and is why such a decode must never be used directly as a system-level control signal; if a clean modulus-10 output is required, a synchronous counter that loads 0000 on the count of 9 should be used instead. The counter's useful sequence is nonetheless the required ten states, repeating every ten clocks.