Question 1 of 6: CMOS Inverter Voltage-Transfer Characteristic
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams — 07-Elec-A5 Electronics, December 2013. Closed book; non-communicating calculator permitted. Six questions of 20 marks; any five constitute a complete paper — all six are solved here as a study resource. Op-amps ideal with ±15 V supplies unless stated; diode forward drop as given per question.
Reference texts. A. Sedra & K. Smith, Microelectronic Circuits, 7th ed. (Oxford) — MOS/BJT amplifiers (ch. 7–9), diode wave-shaping (ch. 4), op-amp circuits (ch. 2), CMOS logic (ch. 14). Cross-checks from C. Sadiku, Fundamentals of Electric Circuits.
Check / source notes. All 16 schematics follow the printed drawings; diode orientations are as drawn (Q5 a/b/d, Q6 b). Q2's data block is internally inconsistent (it labels the BJT NPN yet lists VEB(on), names an RL that is not in the drawing, and gives RE = 1 kΩ while part (a) asks you to sizeRE); assumptions used to resolve these are stated in Q2 per the exam's "state any assumptions" instruction.
Given. A complementary CMOS inverter, thresholds VTn > 0 (NMOS) and VTp < 0 (PMOS); supply VDD. Both devices share the same gate and drain node.
Find. The complete VTC with all critical voltages and the operating region of each transistor.
Figure 1. CMOS inverter VTC. Illustrative matched case (VDD=5 V, VTn=|VTp|=1 V, equal device strength). Five regions I–V are labelled with the mode of each transistor.
Approach. Because there is always exactly one path (pull-up or pull-down) that is "on" in steady state, the logic output rails cleanly to a supply; the transition region is set by the region where both transistors conduct in saturation. Walk vIN from 0 to VDD and classify each device.
Output logic levels (part c). With vIN=0 the NMOS is off and the PMOS is a closed (triode) switch, so no static current flows and the output is pulled fully to the rail: $$V_{OH}=V_{DD}.$$ With vIN=VDD the roles reverse, giving $$\boxed{V_{OH}=V_{DD},\qquad V_{OL}=0}.$$ Full rail-to-rail swing is the hallmark of complementary CMOS — there is no resistive divider to a non-zero low level.
Region map (part e). Increasing vIN from 0 to VDD passes through five regions:
Region
Input range
NMOS M1
PMOS M2
I
$0 \le v_{IN} \lt V_{Tn}$
cut-off
triode
II
$V_{Tn} \le v_{IN} \lt V_M$
saturation
triode
III
$v_{IN} \approx V_M$
saturation
saturation
IV
$V_M \lt v_{IN} \le V_{DD}-|V_{Tp}|$
triode
saturation
V
$v_{IN} \gt V_{DD}-|V_{Tp}|$
triode
cut-off
In regions I and V one device is off, so vOUT sits flat at a rail. Region III is the steep, near-vertical transition where both devices are in saturation and behave as high-gain amplifiers.
Switching threshold VM. At VM both transistors are saturated and carry the same current. Equating drain currents $\tfrac12 k_n(V_M-V_{Tn})^2=\tfrac12 k_p(V_{DD}-V_M-|V_{Tp}|)^2$ and writing $r=\sqrt{k_n/k_p}$,
$$\boxed{V_M=\frac{V_{DD}+V_{Tp}+r\,V_{Tn}}{1+r}}.$$ For a matched inverter ($r=1$, $|V_{Tp}|=V_{Tn}$) this is exactly mid-supply, $V_M=V_{DD}/2$ (2.5 V for the 5 V case drawn).
Logic input levels (part d).VIL and VIH are the two inputs where the incremental gain equals −1 (the edges of the "forbidden" transition band). For the matched inverter the standard results are
$$V_{IL}=\frac{3V_{DD}+2V_{Tn}}{8},\qquad V_{IH}=\frac{5V_{DD}-2V_{Tn}}{8}.$$
For the drawn case: $V_{IL}=2.125\text{ V}$ and $V_{IH}=2.875\text{ V}$.
Noise margins (part b). The margins are the flat "safe" input widths that still resolve to a correct rail:
$$\boxed{NM_L=V_{IL}-V_{OL},\qquad NM_H=V_{OH}-V_{IH}}.$$ Here both equal $2.125\text{ V}$ — a symmetric, robust inverter (each margin is about 42% of VDD).
Q1 — labelled VTC quantities (matched 5 V illustration)
