Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams — 07-Elec-A5 Electronics, December 2013. Closed book; non-communicating calculator permitted. Six questions of 20 marks; any five constitute a complete paper — all six are solved here as a study resource. Op-amps ideal with ±15 V supplies unless stated; diode forward drop as given per question.
Reference texts. A. Sedra & K. Smith, Microelectronic Circuits, 7th ed. (Oxford) — MOS/BJT amplifiers (ch. 7–9), diode wave-shaping (ch. 4), op-amp circuits (ch. 2), CMOS logic (ch. 14). Cross-checks from C. Sadiku, Fundamentals of Electric Circuits.
Check / source notes. All 16 schematics follow the printed drawings; diode orientations are as drawn (Q5 a/b/d, Q6 b). Q2's data block is internally inconsistent (it labels the BJT NPN yet lists VEB(on), names an RL that is not in the drawing, and gives RE = 1 kΩ while part (a) asks you to sizeRE); assumptions used to resolve these are stated in Q2 per the exam's "state any assumptions" instruction.
Find. Small-signal voltage gain (source input, drain output), input resistance at the source, output resistance at the drain.
Figure 5. Common-gate stage: gate AC-grounded by the R1/R2 divider, input at the source (fed by the ideal Ibias source), output at the drain.
Approach. The ideal current source sets ID=2 mA directly. Find the overdrive and hence gm and ro, then apply the common-gate small-signal formulas.
Operating point. The current source fixes $I_D=2$ mA. Neglecting λ for the bias, $\tfrac12 K\,V_{ov}^2=I_D\Rightarrow V_{ov}=\sqrt{2I_D/K}=\sqrt{2\cdot2/1}=2\text{ V}.$
Voltage gain, ro included (part a). For the common-gate stage (input at source, output at drain, drain load RD):
$$\frac{v_o}{v_{in}}=\Big(g_m+\tfrac1{r_o}\Big)(R_D\parallel r_o)=(2.2\text{ mS})(2\text{k}\parallel5\text{k})=(2.2\text{ mS})(1.43\text{ k}\Omega)=\boxed{+3.14}.$$ The gain is positive — the common-gate stage is non-inverting.
Input resistance at the source (part b). Looking into the source with RD as the drain load,
$$R_{in}=\frac{R_D+r_o}{1+g_m r_o}=\frac{2\text{k}+5\text{k}}{1+(2\text{ mS})(5\text{k})}=\frac{7\text{k}}{11}=\boxed{636\ \Omega}.$$ (The ideal Ibias adds no shunt, so this is the amplifier input resistance; it is low, the signature of a common-gate/current-buffer input.)
Output resistance at the drain (part c). The source is degenerated by the ideal current source (infinite resistance), which boosts the drain resistance of M1 to essentially infinity; it therefore drops out and
$$R_o=R_D\parallel\big[r_o(1+g_mR_{source})\big]\Big|_{R_{source}\to\infty}=R_D=\boxed{2\text{ k}\Omega}.$$
Check (second-order λ effect). Retaining (1+λvDS) in the bias lowers Vov to ≈1.62 V and raises gm to ≈2.5 mS (gain ≈3.8, Rin≈524 Ω). The standard practice — ignore λ for bias, keep ro for small signal — is used for the boxed answers.
