Question 2 of 6: Common-Collector (Emitter-Follower) Design
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams — 07-Elec-A5 Electronics, December 2013. Closed book; non-communicating calculator permitted. Six questions of 20 marks; any five constitute a complete paper — all six are solved here as a study resource. Op-amps ideal with ±15 V supplies unless stated; diode forward drop as given per question.
Reference texts. A. Sedra & K. Smith, Microelectronic Circuits, 7th ed. (Oxford) — MOS/BJT amplifiers (ch. 7–9), diode wave-shaping (ch. 4), op-amp circuits (ch. 2), CMOS logic (ch. 14). Cross-checks from C. Sadiku, Fundamentals of Electric Circuits.
Check / source notes. All 16 schematics follow the printed drawings; diode orientations are as drawn (Q5 a/b/d, Q6 b). Q2's data block is internally inconsistent (it labels the BJT NPN yet lists VEB(on), names an RL that is not in the drawing, and gives RE = 1 kΩ while part (a) asks you to sizeRE); assumptions used to resolve these are stated in Q2 per the exam's "state any assumptions" instruction.
Find.RE, RC; the output resistance seen looking into the emitter; and the largest undistorted peak-to-peak emitter swing.
[Figure not reproduced: Figure 2. Emitter follower redrawn from the exam. Collector is AC-grounded by C C (common-collector); signal is taken at the emitter. Treated as NPN (see check note). See the official exam paper.]
Check (assumptions used). The device is taken as NPN (emitter arrow out), so VBE(on) = 0.7 V. The base is returned to ground through RB=100 Ω; the base current IB=IE/(β+1)=19.8 µA drops only 2 mV across RB, so VB ≈ 0. The stray "RL=10 kΩ" and the pre-printed "RE=1 kΩ" in the data block are inconsistent with part (a) asking you to sizeRE; part (a) is answered as a design (they are ignored).
Approach. Fix the DC operating point from the emitter loop, then use the small-signal emitter model $r_e=V_T/I_E$ for the output resistance, and finally bound the swing by the two clipping mechanisms (transistor saturation on the up-swing, cut-off on the down-swing).
Emitter voltage. With VB≈0, $$V_E=V_B-V_{BE(on)}=0-0.7=-0.7\text{ V}.$$
Size RE for IE=2 mA (part a). The emitter resistor carries IE from VE down to the −5 V rail:
$$R_E=\frac{V_E-(-5)}{I_E}=\frac{-0.7+5}{2\text{ mA}}=\boxed{2.15\text{ k}\Omega}.$$
Choose RC (part a). Because CC bypasses the collector to AC ground, RC carries no signal and only sets the DC collector voltage; it must merely keep the transistor active ($V_{CE}\gt V_{CE(sat)}$). With $I_C=\beta I_E/(\beta+1)=1.98$ mA, placing a comfortable $V_{CE}=5$ V puts the collector at $V_C=V_E+5=4.3$ V:
$$R_C=\frac{5-V_C}{I_C}=\frac{5-4.3}{1.98\text{ mA}}\approx\boxed{0.35\text{ k}\Omega}.$$
(Any RC from 0 up to about 2.3 kΩ keeps the device active; 0.35 kΩ leaves generous headroom.)
Output resistance looking into the emitter (part b). The follower divides the source-side resistance by (β+1) and adds re. The base sees $R_B\parallel R_S=100\parallel100=50\ \Omega$, so
$$R_O=r_e+\frac{R_B\parallel R_S}{\beta+1}=12.5+\frac{50}{101}=\boxed{13.0\ \Omega}.$$ This very low output resistance is exactly why the emitter follower is used as a buffer. (At the physical emitter node this RO appears in parallel with RE, giving $R_O\parallel R_E\approx12.8\ \Omega$.)
Maximum undistorted swing (part c). The quiescent emitter sits at −0.7 V. Two limits bound a symmetric (class-A) swing:
Up-swing (collector saturation): the emitter can rise until $V_{CE}=V_{CE(sat)}$, i.e. to $V_C-0.3=4.0$ V — a headroom of $4.0-(-0.7)=4.7$ V.
Down-swing (cut-off): the emitter can fall until IE→0 at the −5 V rail — a headroom of $-0.7-(-5)=4.3$ V.
The smaller limit (cut-off, 4.3 V) governs the symmetric undistorted amplitude, so
$$\boxed{v_{o,\text{pp,max}}=2\times4.3=8.6\text{ V}_{pp}}.$$
