Question 1 of 6: Enhancement-Load NMOS Inverter — Voltage Transfer Characteristic
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, May 2013 — 07-Elec-A5 Electronics. Three hours, closed book; one approved Casio or Sharp calculator permitted. Six questions are printed, each worth 20 marks, and five constitute a complete paper — all six are solved below as a study resource. Op-amps are ideal with ±15 V supplies unless stated otherwise.
Reference texts. A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (Oxford): Ch. 5–7 (MOSFET and BJT amplifiers, common-emitter and common-gate stages), Ch. 4 (diode limiters, clamps and rectifiers), Ch. 13–14 (CMOS/NMOS inverter VTC and noise margins), and Ch. 2 (op-amp precision rectifiers and slew rate).
Question 1: Enhancement-Load NMOS Inverter — Voltage Transfer Characteristic (20 marks)
Given. An enhancement-load NMOS inverter (Fig. Q1): driver M1 with its gate driven by $v_{IN}$, and load $M_2$ with its gate tied to $+V_{DD}$. Both transistors are identical (same threshold $V_t$ and same $k=\mu_n C_{ox}(W/L)$). No numeric $V_{DD}$ or $V_t$ is supplied.
Find. The complete VTC with every logic level and noise margin marked, plus the operating mode of each device in every region.
Q1 circuit: enhancement-load NMOS inverter. M2 (load) has its gate tied to +VDD; M1 (driver) gate is the input v_IN. Output taken at the common drain/source node.
Approach. Because no numbers are given, work the levels symbolically from the drain-current equalities of the two devices, then draw the VTC for representative values.
Load is always saturated; it fixes the output-high level. With its gate at $V_{DD}$, the load $M_2$ has $v_{GS2}=V_{DD}-v_{OUT}$ and $v_{DS2}=V_{DD}-v_{OUT}=v_{GS2}$, so $v_{DS2}\ge v_{GS2}-V_t$ — $M_2$ is in saturation whenever it conducts. It stops conducting when $v_{GS2}=V_t$, i.e. when the output reaches $$\boxed{V_{OH}=V_{DD}-V_t}$$ This one-threshold loss below $V_{DD}$ is the hallmark of the saturated enhancement load.
Region I — input low. For $v_{IN}\lt V_t$ the driver $M_1$ is cut off. No current flows, the load pulls the output up, and $v_{OUT}=V_{OH}=V_{DD}-V_t$. Mode: M1 cut-off, M2 saturated.
Region II — both saturated. For $V_t\lt v_{IN}\lt \tfrac{V_{DD}+V_t}{2}$ both devices saturate. Equating currents, $\tfrac{1}{2}k(v_{IN}-V_t)^2=\tfrac{1}{2}k(V_{DD}-v_{OUT}-V_t)^2$; with identical devices this gives $v_{IN}-V_t=V_{DD}-v_{OUT}-V_t$, hence $$\boxed{v_{OUT}=V_{DD}-v_{IN}}$$ a straight line of slope exactly $-1$. Mode: both saturated.
Transition into triode. The driver leaves saturation when $v_{DS1}=v_{OUT}=v_{IN}-V_t$. Combined with $v_{OUT}=V_{DD}-v_{IN}$ this occurs at $v_{IN}=\tfrac{V_{DD}+V_t}{2}$, $v_{OUT}=\tfrac{V_{DD}-V_t}{2}$.
Region III — driver in triode. For $v_{IN}\gt \tfrac{V_{DD}+V_t}{2}$, equating the triode driver to the saturated load, $$k\!\left[(v_{IN}-V_t)v_{OUT}-\tfrac{1}{2}v_{OUT}^2\right]=\tfrac{1}{2}k\,(V_{DD}-v_{OUT}-V_t)^2 .$$ Evaluated at the largest logic input $v_{IN}=V_{OH}=V_{DD}-V_t$ this yields the output-low level $V_{OL}$ (small but not zero). Mode: M1 triode, M2 saturated.
Input thresholds and noise margins. Because Region II has slope exactly $-1$ throughout, the two unity-gain points are its endpoints: $V_{IL}=V_t$ and $V_{IH}=\tfrac{V_{DD}+V_t}{2}$. Then $NM_H=V_{OH}-V_{IH}$ and $NM_L=V_{IL}-V_{OL}$.
Drawing the VTC for the common textbook values $V_{DD}=5\ \text{V}$, $V_t=1\ \text{V}$ (chosen only to give the curve a scale) gives $V_{OH}=4\ \text{V}$, the transition at $(3,2)$, and $V_{OL}\approx1.44\ \text{V}$:
Q1 VTC (drawn for representative VDD=5 V, Vt=1 V; the paper gives no numbers). I: M1 cut-off, M2 saturated, v_OUT=V_OH=VDD-Vt. II: both saturated, v_OUT=VDD-v_IN (slope -1). III: M1 triode, M2 saturated, v_OUT falls to V_OL. Unity-gain points bound region II.
Check: the exam supplies no numeric $V_{DD}$ or $V_t$, so the VTC is drawn for representative values ($V_{DD}=5$ V, $V_t=1$ V). The labelled levels and region modes — not the specific numbers — are the graded content. Note the low margin $NM_L=V_{IL}-V_{OL}=1-1.44\lt 0$: the saturated enhancement load has a poor (high) $V_{OL}$ and hence a weak low-side noise margin, which is exactly why depletion-load and CMOS inverters are preferred.