Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, May 2013 — 07-Elec-A5 Electronics. Three hours, closed book; one approved Casio or Sharp calculator permitted. Six questions are printed, each worth 20 marks, and five constitute a complete paper — all six are solved below as a study resource. Op-amps are ideal with ±15 V supplies unless stated otherwise.
Reference texts. A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (Oxford): Ch. 5–7 (MOSFET and BJT amplifiers, common-emitter and common-gate stages), Ch. 4 (diode limiters, clamps and rectifiers), Ch. 13–14 (CMOS/NMOS inverter VTC and noise margins), and Ch. 2 (op-amp precision rectifiers and slew rate).
Find. The small-signal voltage gain $v_o/v_{in}$, the input resistance $R_{in}$ (into the source), and the output resistance $R_o$ (at the drain).
[Figure not reproduced: Q6 circuit (redrawn): common-gate amplifier. R1/R2 set the DC gate voltage; Ibias fixes the drain current at 2 mA; the signal enters the SOURCE through C1 and leaves the DRAIN through C2. RD is the drain load. See the official exam paper.]
Approach. Get the operating-point transconductance and output resistance from $I_{bias}$, then apply the common-gate small-signal relations (input at the source, output at the drain, gate at AC ground).
Small-signal parameters. With $I_D=I_{bias}=2\ \text{mA}$: overdrive $V_{ov}=\sqrt{2I_D/K}=\sqrt{2(2)/1}=2\ \text{V}$, so $$g_m=K V_{ov}=\sqrt{2K I_D}=2\ \text{mA/V},\qquad r_o=\frac{1}{\lambda I_D}=\frac{1}{0.1\times2\ \text{mA}}=5\ \text{k}\Omega.$$ (The gate bias $V_G=V_{DD}R_2/(R_1+R_2)=3.33$ V simply keeps $M_1$ in saturation.)
(a) Voltage gain. For the common-gate stage (open output), $$\frac{v_o}{v_{in}}=\frac{g_m+1/r_o}{1/R_D+1/r_o}=(1+g_m r_o)\frac{R_D}{R_D+r_o}.$$ Substituting, $$\frac{v_o}{v_{in}}=(1+2\times5)\frac{2\ \text{k}}{2\ \text{k}+5\ \text{k}}=11\times0.286=\boxed{3.14\ \text{V/V}}$$ (non-inverting — the common gate does not invert).
(b) Input resistance. Looking into the source with $R_D$ as the drain load, $$R_{in}=\frac{R_D+r_o}{1+g_m r_o}=\frac{2\ \text{k}+5\ \text{k}}{11}=\boxed{636\ \Omega}.$$ The ideal $I_{bias}$ source ($\infty$ resistance) in parallel does not load it. (Neglecting $r_o$, $R_{in}\approx1/g_m=500\ \Omega$.)
(c) Output resistance. Zeroing the ideal signal source shorts the source node ($R_{sig}=0$), so the resistance looking into the drain is just $r_o$, in parallel with $R_D$: $$R_o=R_D\parallel r_o=2\ \text{k}\parallel5\ \text{k}=\boxed{1.43\ \text{k}\Omega}.$$
